efficient switching from one program to another, as
well as for the relocation of programs in storage. To
the prob1em programmer, the supervisory program
and the equipment are indistinguishable.
System Alerts
The interruption system permits the CPU automatically
to change state as a result of conditions arising out­
side of the system, in 1/0 units, or in the CPU itself.
Interruption switches the CPU from one program to
another by changing not only the instruction address
but all essential machine-status information.
A storage protection feature permits one program to
be preserved when another program erroneously at­
tempts to store information in the area assigned to
the first program. Protection does not cause any loss
of performance. Storage operations initiated from the CPU, as well as those initiated from a channel, are sub­
ject to the protection procedure.
Programs are checked for correct instructions and
data as they are executed. This policing-action identi­
fies and separates program errors and machine errors.
Thus, program errors cannot create machine checks
since each type of error causes a unique interruption.
In addition to an interruption due to machine mal­
function, the information necessary to identify the
error is recorded automatically in a predetermined
storage location. This procedure appreciably reduces
the mean-time to repair a machine fault. Moreover,
operator errors are reduced by minimizing the active
manual controls. To reduce accidental operator errors,
operator consoles are 110 devices and function under
control of the system program.
Multisystem Operation Several models of System/360 can be combined into
one multisystem configuration. Three levels of com­
munication between CPu's are available. Largest in ca­
pacity, and moderately fast in response, is communi­
cations by means of shared 1/0 device, for example,
a disk file. Faster transmission is obtained by direct
connection between the channels of two individual
systems. Finally, storage may be shared on some
models between two cpu's, making information ex­
change possible at storage speeds. These modes of
communication are supplemented by allowing one CPU to be interrupted by another CPU and by making direct
status information available from one CPU to another.
Channels provide the data path and control for 1/0 devices as they communicate with the CPU. In general,
channels operate asynchronously with the CPU and, in
some cases, a single data path is made up of several
sub channels. When this is the case, the single data
path is shared by several low-speed devices, for ex­
ample, card readers, punches, printers, and terminals.
This channel is called a multiplexor channel. Chan­
nels that are not made up of several such subchannels
can operate at higher speed than the multiplexor
channels and are called selector channels. In every
case, the amount of data that comes into the channel
in parallel from an 110 device is a byte. All channels
or subchannels operate the same and respond to the
same 110 instructions and commands.
Each 110 device is connected to one or more chan­
nels by an 110 interface. This 110 interface allows at­
tachment of present and future 110 devices without
altering the instruction set or channel function. Con­
trol units are used where necessary to match the in­
ternal connections of the 110 device to the interface.
Flexibility is enhanced by optional access to a control
unit or dcvice from either of two channels.
Technology System/360 employs solid-logic integrated compo­
nents, which in themselves provide advanced equip­
ment reliability. These components are also faster and
smaller than previous components and lend them­
selves to automated fabrication.
The basic structure of a System/360 consists of main
storage, a central processing unit (cPu), the selector
and multiplexor channels, and the input! output de­
vices attached to the channels through control units.
It is possible for systems to communicate with each
other by means of shared I/O devices, a channel, or
shared storage. Figure 1 shows the basic organization
of a single system.
Main Storage Storage units may be either physically integrated with
the CPU or constructed as stand-alone units. The stor­
age cycle is not directly related to the internal cycling
of the CPU, thus permitting selection of optimum stor­
age speed for a given word size. The physical differ­
ences in the various main-storage units do not affect
the logical structure of the system.
Fetching and storing of data by the CPU are not af­
fected by any concurrent I/O data transfer. If an I/O operation refers to the same storage location as the CPU operation, the accesses are granted in the se­
quence in which they are requested. If the first refer­
ence changes the contents of the location, any sub­
sequent storage fetches obtain the new contents. Con­
current I/O and CPU references to the same storage
location never cause a machine-check indication.
- Control '-- System Structure
Information Formats
The system transmits information between main stor­
age and the CPU in units of eight bits, or a multiple
of eight bits at a time. An eight-bit unit of information
is called a byte, the basic building block of all formats.
A ninth bit, the parity or check bit, is transmitted
with each byte and carries parity on the bytes. The
parity bit cannot be affected by the program; its only
effect is to cause an interruption when a parity error
is detected. References to the size of data fields and
registers, therefore, exclude the associated parity bits.
All storage capacities are expressed in number of bytes
provided, regardless of the physical word size actually
Bytes may be handled separately or grouped to­
gether in fields. A halfword is a group of two consecu­
tive bytes and is the basic building block of instruc­
tions. A word is a group of four consecutive bytes; a
double word is a field consisting of two words (Figure
2). The location of any field or group of bytes is spe­
cified by the address of its leftmost byte.
The length of fields is either implied by the oper­
ation to be performed or stated explicitly as part of
the instruction. When the length is implied, the in­
formation is said to have a fixed length, which can be
either one, two, four, or eight bytes.
When the length of a field is not implied by the Input/ I 1 - Output c Unit c f---t - Device ....c: U f-----t c-- .... f---i Q) 1 f-----t ""5 f---i ::E f----i Central Processing t- Input/ Unit Control t-- I-- Output f------\ Unit t- Device W c f---t t-- C c f---t ....c: U --I .... .8 --I u Q) --I W Vl --I Figure 1. IBM System/360 Basic Logical Structure
System Structure 7
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