Shift Riglht Double SRDI. RS
7 8 11 12 1516 1920 31
The double-length first operand is shifted right the
number of bits specified by the second operand ad­
The R L field of the instruction specifies an even/odd
pair of registers and must contain an even register ad­
dress. An odd value for Rl is a specification exception
and causes a program interruption. The second oper­
and address is not used to address data; its low-order
six bits indicate the number of bit positions to be
shifted. The remainder of the address is ignored.
All 64 bits of the even/odd register pair specified
by Rl participate in the shift. Low-order bits are
shifted out of the odd-numbered register without in­
spection and are lost. Zeros are supplied to the va­
cated high-order positions of the registers. Condition Code: The code remains unchanged.
Program Interruptions: S pedfica tion
Programming Note
The logical shifts differ from the arithmetic shifts in
that the high-order bit participates in the shift and is
not propagated, the condition code is not changed,
and no overflow occurs.
Logical Operation Exceptions
Exceptional instructions, data,or results cause a pro­
gram interruption. When the interruption occurs, the
current psw is stored as an old psw and a new psw 60 is obtained. The interruption code in the old psw
identifies the cause of the interruption. The following
exceptions cause a program interruption in logical op­
Operation: The decimal feature is not installed, and
the instruction is EDIT or EDIT AND MARK. The opera­
tion is suppressed. Therefore, the condition code and
data in registers and storage remain unchanged.
Protection: The storage key of a result location in
storage does not match the protection key in the psw.
The operation is suppressed. Therefore, the condition
code and data in registers and storage remain un­
changed. The only exceptions are the variable-length
storage-to-storage operations, which are terminated.
For terminated operations, the result data and con­
dition code, if affected, are unpredictable and should
not be used for further computation.
Addressing: An address designates a location out­
side the available storage for the installed system. The
operation is terminated. The result data and the con­
dition code, if affected, are unpredictable and should
not be used for further computation.
Specification: A fullword operand in a storage-to­
register operation is not located on a 32-bit boundary
or an odd register address is specified for a pair of
general registers containing a 64-bit operand. The op­
eration is suppressed. Therefore, the condition code
and data in registers and storage remain unchanged.
Data: A digit code of the second operand in EDIT or
EDIT AND MARK is invalid. The operation is terminated.
The result data and the condition code are unpredict­
able and should not be used for further computation. Operand addresses are tested only when used to ad­
dress storage. Addresses used as a shift amount are
not tested. Similarly, the address generated by the use
of LOAD ADDRESS is not tested. The address restrictions
do not apply to the components from which an ad­
dress is generated -the contents of the Dl and D2
fields, and the contents of the registers specified by
X 2 , B1, and B
Instructions are performed by the central process­
ing unit primarily in the sequential order of their
locations. A departure from this normal sequential
operation may occur when branching is performed.
The branching instructions provide a means for mak­
ing a two-way choice, to reference a subroutine, or to ,repeat a segment of coding, such as a loop.
Branching is performed by introducing a branch ad­
dress as a new instruction address.
The branch address may be obtained from one of
the general registers or it may be the address specified
by the instruction. The branch address is independent
of the updated instruction address.
The detailed operation of branching is determined
by the condition code which is part of the program
status word (psw) or by the results in the general reg­
isters which are specified in the loop-closing opera­
During a branching operation, the rightmost half of
the psw, including the updated instruction address,
may be stored before the instruction address is re­
placed by the branch address. The stored information
may be used to link the new instruction sequence with
the preceding sequence.
The instruction EXECUTE is grouped with the branch­
ing instructions. The branch address of EXECUTE desig­
nates a single instruction to be inserted in the instruc­
tion sequence. The updated instruction address norm­
ally is not changed in this operation, and only the in­
struction located at the branch address is executed.
All branching operations are provided in the stand­
ard instruction set.
Normal Sequential Operation
Normally, operation of the CPU is controlled by in­
structions taken in sequence. An instruction is fetched
from a location specified by the instruction-address field of the psw. The instruction address is increased
by the number of bytes of the instruction to address
the next instruction in sequence. This new instruction­
address value, called the updated instruction address,
replaces the previous contents of the instruction-ad­
dress field in the psw. The current instruction is exe­
cuted, and the same steps are repeated, using the up­
dated instruction address to fetch the next instruction.
Instructions occupy a halfword or a multiple there­
of. An instruction may have up to three halfwords.
The number of halfwords in an instruction is specified
by the first two instruction bits. A 00 code indicates a
halfword instruction, codes 01 and 10 indicate a two­
halfword instruction, and code 11 indicates a three­
halfword instruction.
Hallword format I OpCode o 78 15
Two-Ha/fword format I Op Code
Three-Ha/fword format I Op Code
Bl I o 7 8 1516 1920 3132
Storage wraps around from the maximum address­
able storage location, byte location 16,777,215, to byte
location O. An instruction having its last halfword at
the maximum storage location is followed by the in­
struction at address O. Also, a multiple-halfword in­
struction may straddle the upper storage boundary; no
special indication is given in these cases.
Conceptually, an instruction is fetched from storage
after the preceding operation is completed and before
execution of the current operation, even though physi­
cal storage word size and overlap of instruction execu­
tion with storage access may cause actual instruction
fetching to be different.
A change in the sequential operation may be caused
by branching, status-switching, interruption, or man­
ual intervention. Sequential operation is initiated and
terminated from the system control panel.
Branching 61
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