Logical Operations
A set of instructions is provided for the logical ma­ nipulation of data. Generally, the operands are treated
as eight-bit bytes. In a few cases the left or right four
bits of a byte are treated separately or operands are
shifted a bit at a time. The operands are either in
storage or in the general register. Some operands are
introduced from the instruction stream.
Processing of data in storage proceeds left to right
through fields which may start at any byte position. In
the general registers, the processing, as a rule, in­ volves the entire register contents.
Except: for the editing instructions, data are not
treated as numbers. Editing provides a transformation
from packed decimal digits to alphanumeric charac­ ters.
The set of logical operations includes moving, com­ paring, bit connecting, bit testing, translating, editing,
and shift operations. All logical operations other than
editing are part of the standard instruction set. Edit­ ing instructions are pali of the decimal feature.
The condition code is set as a result of all logical
comparing, connecting, testing, and editing operations.
Data Format
Data reside in general registers or in storage or are
introduced from the instruction stream. The data size
may be a single or double word, a single character, or
variable in length. When two operands participate
they have equal length, except in the editing instruc­ tions. Fixed-Lenuth Logical Information Logical Data
31
Data in general registers normally occupy all 32 bits.
Bits are treated uniformly, and no distinction is made
between sign and numeric bits. In a few operations,
only the low-order eight bits of a register participate,
leaving the remaining 24 bits unchanged. In some
shift operations, 64 bits of an even/odd pair of regis­ ters participate. 50 The LOAD ADDRESS introduces a 24-bit address into
a general register. The high-order eight bits of the
register are made zero.
In storage-to-register operations, the storage data
occupy either a word of 32 bits or a byte of eight bits.
The word must be located on word boundaries, that
is, its address must have the two low-order bits zero.
Variable-Length Logical Information
Character Character I Character
16
In storagc-to-storage operations, data have a variable
field-length format, starting at any byte address and
continuing for up to a total of 256 bytes. Processing
is left to right. Operations introducing data from the instruction
stream into storage, as immediate data, are restricted
to an eight-bit byte. Only one byte is introduced from
the instruction stream, and only one byte in storage
participates. Use of general register 1 is implied in TRANSLATE AND TEST and EDIT AND MARK. A 24-bit address may be
placed in this register during these operations. The TRANSLATE AND TEST also implies general register 2.
The low-order eight bits of register 2 may be replaced
by a function byte during a translate-and-test oper­ ation.
Editing requires a packed decimal field and gen­ erates zoned decimal digits. The digits, signs, and
zones are recognized and generated as for decimal
arithmetic. Otherwise, no internal data structure is re­ quired, and all bit configurations are considered valid.
The translating operations use a list of arbitrary
values. A list provides a relation between an argument
(the quantity used to reference the list) and the
function (the content of the location related to the
argument). The purpose of the translation may be to
convert data from one code to another code or to per­ form a control function.
A list is specified by an initial address -the address
designating the leftmost byte location of the list. The
byte from the operand to be translated is the argu­ ment. The actual address used to address the list is
obtained by adding the argument to the low-order po-

sitions of the initial address. As a consequence, the list
contains 256 eight-bit function bytes. In cases where
it is known that not all eight-bit argument values will
occur, it may be possible to reduce the size of the list.
In a storage-to-storage operation, the operand fields
may be defined in such a way that they overlap. The
effect of this overlap depends upon the operation.
When the operands remain unchanged, as in COMPARE or TRANSLATE AND TEST, overlapping does not affect
the execution of the operation. In the case of MOVE, EDIT, and TRANSLATE, one operand is replaced by new
data, and the execution of the operation may be af­
fected by the amount of overlap and the manner in
which data are fetched or stored. For purposes of
evaluating the effect of overlapped operands, consider
that data are handled one eight-bit byte at a time. All
overlapping fields are considered valid but, in editing,
overlapping fields give unpredictable results.
Condition Code
The results of most logical operations are used to set
the condition code in the psw. The LOAD ADDRESS, IN­ SERT CHARACTERS, STORE CHARACTER, TRANSLATE, and
the moving and shift operations leave this code un­
changed. The condition code can be used for decision­
making by subsequent branch-on-condition instruc­
tions.
The condition code can be set to reHect five types
of results for logical operations: For COMPARE LOGICAL the states 0, 1, or 2 indicate that the first operand is
equal, low, or high.
For the logical-connectives, the states ° or 1 indi­
cate a zero or nonzero result field.
For TEST UNDER MASK, the states 0, 1, or 3 indicate
that the selected bits are all-zero, mixed zero and one,
or all-one,
For TRANSLATE AND TEST, the states 0, 1, or 2 indi­
cate an all-zero function byte, a nonzero function byte
with the operand incompletely tested, or a last func­
tion byte nonzero.
For editing the states 0, 1, or 2 indicate a zero, less
than zero, or greater than zero content of the last re­
sult field. CONDITION CODE SETTING FOR LOGICAL OPEHA TIONS 0 1 2 3
And zero not zero
Compare Logical equal low high
Edit zero < zero > zero
Edit and Mark zero < zero > zero
Exclusive Or zero not zero Or zero not zero
Test Under Mask zero mixed one
Translate and Test zero incomplete complete
Instruction format
Logical instructions use the following five formats:
RR Format I Op Code R1 R2
o 78 1112 15
RX Format Op Code R1
X
2
B2
7 8 11 12 1516 1920 31
R5 Format Op Code R1 R3 B2
7 8 11 12 1516 1920 31
51 Format Op Code
7 8 15 16 1920 31 5S Format Op Code L
B1 I B2 IJ3J 78 1516 1 9 20 31 32 35 36 47
In the RR, RX, and RS formats, the content of the regis­
ter specified by Rl is called the first operand.
In the SI and ss formats, the content of the general
register specified by Bl is added to the content of the
Dl field to form an address. This address deSignates
the leftmost byte of the first operand field. The num­
ber of bytes to the right of this first byte is specified
by the L field in the ss format. In the SI format the size is one byte.
In the RR format, the R2 field specifies the register
containing the second operand. The same register may
be specified for the first and second operand.
In the RX format, the contents of the general regis­
ters specified by the X2 and B2 fields arc added to the
content of the D2 field to form the address of the sec­
ond operand.
In the RS format, used for shift operations, the con­
tent of the general register specified by the B2 field
is added to the content of the D2 field. This sum is not
used as an address but specifies the number of bits of
the shift. The RH field is ignored in the shift oper­
ations.
Logical Operations 51