Input/Output Interruption
The1/ () interruption provides a means by which the CPU responds to signals from I/O devices.
A request for anI/O interruption may occur at any
time,and more than one request may occur at the
sametime. The requests are preserved in the I/O section until accepted by the CPU. Priority is estab
lished among requests so that only one interruption
request is processed at a time.
AnI/O interruption can occur only after execution
of the current instruction is completed and while theCPU is interruptable for the channel presenting the
request. Channels are masked by system mask bits0-6. Interruptions masked off remain pending.
TheI/O interruption causes the old psw to be stored
atlocation 56 and causes the channel status word as
sociated with the interruption to be stored at location
64.Subsequently, a new psw is loaded from location 120. The interruption code in the old psw identifies the
channel and device causing the interruption in bits
21-23 and 24-31, respectively. Bits16-20 of the old psw
are made zero. The instruction-length code is unpre
dictable.
Program Interruption
Exceptions resulting from improper specification or
use of instructions and data cause a program interrup
tion.
The current instruction is completed, terminated, or
suppressed.Only one program interruption occurs for
a given instruction and is identified in the old psw.
The occurrence of a program interruption docs not
preclude the simultaneous occurrence of other pro
gram-interruption causes. Which of several causes is
identified may vary from one occasion to the next and
from one model to another.
A program interruption can occur only when the
corresponding mask bit, if any, is one. When the mask
bit is zero, the interruption is ignored.Program inter
ruptions do not remain pending.Program mask bits
36-39 permit masking of four of the 15 interruption
causes.
The program interruption causes the old psw to be
stored at location40 and a new psw to be fetched
from location104. The cause of the interruption is identified by inter
ruption-code bits 28-31. The remainder of the interrup
tion code, bits 16-27 of the PSW, are made zero. The
instruction-length code indicates the length of the
preceding instruction in halfwords. For a few cases,
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the instruction length is not available. These cases are
indicated by codeO. A description of the individual program exceptions
follows. The application of these rules to each class of
instructions is further described in the applicable sec
tions.Some of the exceptions listed may also occur in
operations executed byI/O channels. In that event, the
exception is indicated in the channel status word
stored with theI/O interruption (as explained under "Input/Output Operations"). Operation Exception
When an operation code is not assigned or the as
signed operation is not available on the particular
model, an operation exception is recognized. The op
eration is suppressed.
The instruction-length code is 1, 2, or 3.
Privileged-Operation Exception
When a privileged instruction is encountered in the
problem state, a privileged-operation exception is rec
ognized. The operation is suppressed.
The instruction-length code is 1 or 2.
Execute Exception
When the subject instruction of EXECUTE is another
EXECUTE, an execute exception is recognized. The
operation is suppressed.
The instruction-length code is 2.
Protection Exception
When the storage key of a result location does not
match the protection key in thePSW, a protection ex
ception is recognized.
The operation is suppressed, except in the case ofSTORE MULTIPLY, READ DIRECT, and variable-length op
erations, which are terminated.
The instruction-length code is0, 2, or 3.
Addressing Exception
When an address specifies any part of data, an in
struction, or a control word outside the available
storage for the particular installation, an addressing
exception is recognized.
The operation is terminated for an invalid data
address. Data in storage remain unchanged, except
when designated by valid addresses. The operation is
suppressed for an invalid instruction address.
The instruction-length code normally is 1, 2 or 3;
but may be0 in the case of a data address.
The
A request for an
time,
same
lished among requests so that only one interruption
request is processed at a time.
An
of the current instruction is completed and while the
request. Channels are masked by system mask bits
The
at
sociated with the interruption to be stored at location
64.
channel and device causing the interruption in bits
21-23 and 24-31, respectively. Bits
are made zero. The instruction-length code is unpre
dictable.
Program Interruption
Exceptions resulting from improper specification or
use of instructions and data cause a program interrup
tion.
The current instruction is completed, terminated, or
suppressed.
a given instruction and is identified in the old psw.
The occurrence of a program interruption docs not
preclude the simultaneous occurrence of other pro
gram-interruption causes. Which of several causes is
identified may vary from one occasion to the next and
from one model to another.
A program interruption can occur only when the
corresponding mask bit, if any, is one. When the mask
bit is zero, the interruption is ignored.
ruptions do not remain pending.
36-39 permit masking of four of the 15 interruption
causes.
The program interruption causes the old psw to be
stored at location
from location
ruption-code bits 28-31. The remainder of the interrup
tion code, bits 16-27 of the PSW, are made zero. The
instruction-length code indicates the length of the
preceding instruction in halfwords. For a few cases,
78
the instruction length is not available. These cases are
indicated by code
follows. The application of these rules to each class of
instructions is further described in the applicable sec
tions.
operations executed by
exception is indicated in the channel status word
stored with the
When an operation code is not assigned or the as
signed operation is not available on the particular
model, an operation exception is recognized. The op
eration is suppressed.
The instruction-length code is 1, 2, or 3.
Privileged-Operation Exception
When a privileged instruction is encountered in the
problem state, a privileged-operation exception is rec
ognized. The operation is suppressed.
The instruction-length code is 1 or 2.
Execute Exception
When the subject instruction of EXECUTE is another
EXECUTE, an execute exception is recognized. The
operation is suppressed.
The instruction-length code is 2.
Protection Exception
When the storage key of a result location does not
match the protection key in the
ception is recognized.
The operation is suppressed, except in the case of
erations, which are terminated.
The instruction-length code is
Addressing Exception
When an address specifies any part of data, an in
struction, or a control word outside the available
storage for the particular installation, an addressing
exception is recognized.
The operation is terminated for an invalid data
address. Data in storage remain unchanged, except
when designated by valid addresses. The operation is
suppressed for an invalid instruction address.
The instruction-length code normally is 1, 2 or 3;
but may be