Fixed Lengl'h Logical Information I Logical Data Variable-Length Logical Information I Character I Character 16 Character Figure 10. Fixed-Length and Variable-Length Logical
Information
31
( EBCDIC) (Figure 11) or the American StandardCode for Information Interchange (ASCII) extcnded to eight
bits (Figure 12).
The preferred codes do not have a graphic defined
for all 256 eight-bit codes. When it is desirable to rep
resent all possible bit patterns, a hexadecimal repre
sentation may be used instead of the preferred eight
bit code. The hexadecimal representation uses one
graphic for a four-bit code, and therefore, two graph
ics for an eight-bit byte. The graphics0-9 are used
for codes0000-1001; the graphics A-F are used for
codes1010-1111. Bit Positions -,----. .. 01 L U:-
2
-3--
00
------, 4567 00 01 10 11 00 01 10 11 0000 NUL BLANK & - 0001 / 0010 0011 0100 PF RES BYP PN 0101 HT NL LF RS 0110 LC .BS EOB UC - 0111 DEL IDL PRE EOT 1000 -- 1001 , " 1010 ? ! : 1011 $ ,
#1100 4--- * % @ 1101 ( ) ry-.. I 1110 + ;
-
=
1111$ C7 +
j
-
Figure 11. Extended Binary-Coded-Decimal InterchangeCode 12
Program Execution
TheCPU program consists of instructions, index words,
and control words specifying the operations to be per
formed. This information resides in main storage and
general registers, and may be operated upon as data.Instruction Format
The length of an instruction format can be one, two,
or three halfwords. It is related to the number of stor
age addresses necessary for the operation. An instruc
tion consisting of only one halfword causes no refer
ence to main storage. A two-halfword instruction pro
vides one storage-address specification; a three-half
word instruction provides two storage-address specifi
cations. All instructions must be located in storage on
integral boundaries for halfwords. Figure 13 shows
five basic instruction formats.
The five basic instruction formats are denoted by
the format codes RR, RX,RS, SI, and ss. The format
codes express, in general terms, the operation to be
performed. RR denotes a register-to-register operation;
RX, a register-to-indexed-storage operation;RS, a regis- 00 01 10 11 00 01 10 11 > < :j: 0 a
i
A J 1
b k s B KS 2
cI t C L T 3
d m u D
M U
4
e n v E NV 5
f0 w F 0 W 6
9P x G P X 7
h q y H
Q Y 8
i r zI R Z 9 1----- _._---
Information
31
( EBCDIC) (Figure 11) or the American Standard
bits (Figure 12).
The preferred codes do not have a graphic defined
for all 256 eight-bit codes. When it is desirable to rep
resent all possible bit patterns, a hexadecimal repre
sentation may be used instead of the preferred eight
bit code. The hexadecimal representation uses one
graphic for a four-bit code, and therefore, two graph
ics for an eight-bit byte. The graphics
for codes
codes
2
-3--
00
------,
#
-
=
1111
j
-
Figure 11. Extended Binary-Coded-Decimal Interchange
Program Execution
The
and control words specifying the operations to be per
formed. This information resides in main storage and
general registers, and may be operated upon as data.
The length of an instruction format can be one, two,
or three halfwords. It is related to the number of stor
age addresses necessary for the operation. An instruc
tion consisting of only one halfword causes no refer
ence to main storage. A two-halfword instruction pro
vides one storage-address specification; a three-half
word instruction provides two storage-address specifi
cations. All instructions must be located in storage on
integral boundaries for halfwords. Figure 13 shows
five basic instruction formats.
The five basic instruction formats are denoted by
the format codes RR, RX,
codes express, in general terms, the operation to be
performed. RR denotes a register-to-register operation;
RX, a register-to-indexed-storage operation;
i
A J 1
b k s B K
c
d m u D
M U
4
e n v E N
f
9
h q y H
Q Y 8
i r z