When a programming error occurs in the inform a -
tion placed in the CAW or ccw and the addressed
channel or sub channel is working, either condition
code 1 or 2 may be set, depending on the model.
Similarly, either code 1 or 3 may be set when a pro­
gramming error occurs and a part of the addressed I/O system is not operational.
When a programming error occurs and the ad­
dressed device contains an interruption condition,
with the channel and sub channel in the available
state, START I/O mayor may not clear the interruption
condition, depending on the type of error and the
model. If the instruction has caused the device to be
interrogated, as indicated by the presence of the busy
bit in the csw, the interruption condition has been
cleared, and the csw contains program check, as well
as the status from the device.
When the channel detects several error conditions,
all conditions may be indicated or only one may ap­
pear in the csw, depending on the condition and the
model. Equipment Errors Parity errors detected by the channel on data sent to
or received from the I/O device on some models cause
the current operation to be terminated. When the
channel and the CPU share common equipment, parity
errors on data may cause malfunction reset to be per­
formed. The recovery procedure in the channel and
subsequent state of the sub channel upon a malfunc­
tion reset depend on the model.
Detection of channel control check or interface con­
trol check causes the current operation, if any, to be
immediately terminated and causes the channel to per­
form the malfunction-reset function. The recovery pro­
cedure in the channel and the subsequent state of the
sub channel upon a malfunction reset depend on the
The contents of the csw, as well as the address in
the psw identifying the I/O device, are unpredictable
upon the detection of a channel-control-check con­
Execution of malfunction reset in the channel de­
pends on the type of error and model. It may cause
all operations in the channel to be terminated and all
operational subchannels to be reset to the available
state. The channel may send the malfunction-reset
signal to the device connected to the channel at the
time the malfunctioning is detected, or a channel shar­
ing common equipment with the CPU may send the
system-reset signal to all devices attached to the chan­
The method of processing a request for interruption
due to equipment malfunctioning, as indicated by the
presence of the channel-data-check, channel-control­
check, and interface-control-check conditions, depends
on the model. In channels sharing common equipment
with the CPU, malfunctioning detected by the channel
may be indicated by the machine-check interruption.
Alphabetic List of Instructions
The listings in the TYPE and EXCEPTIONS columns mean: Compare Logical CLR RR C 15
A Addressing exception Compare Logical CL RX C A,S 55 C Condition code is set Compare Logical CLI SI C A 95
D Data exception Compare Logical CLC SS C A D5
DF Decimal-overflow exception Compare (Long) CDR RRF,C S 29
DK Decimal-divide exception Compare (Long) CD HXF,C A,S 69
E Exponen t -overflow exception Compare (Short) CER RRF,C S 39
EX Execute exception Compare (Short) CE RXF,C A,S 79
F Floating-point feature Convert to Binary CVB RX A,S,D, IK 4F
FK Floating-point divide exception Convert to Decimal CVD RX P,A,S 4E
IF Fixed-point overflow exception
Diagnose SI M, A,S 83
IK Fixed-point divide exception
Divide DR RR S, IK ID
L New condition code loaded
Divide D RX A,S, IK 5D LS Significance exception
Divide Decimal DP SS T P,A,S,D, DK FD
M Privileged-operation exception
Divide (Long) NDDR RRF S,U,E,FK 2D
N Normalized operation
Divide (Long) NDD RXF A,S,U,E,FK 6D P Protection exception
Divide (Short) NDER RRF S,U,E,FK 3D S Specification exception
Divide (Short) NDE RXF A,S,U,E,FK 7D
T Decimal feature
Edit ED SS T,C P,A, D, DE U Exponent-underflow exception
Edit and Mark EDMK SS T,C P,A, D, DF Y Direct control feature
Exclusive OR XR RR C 17 Z Protection feature
Exclusive OR X RX C A,S 57
Exclusive OR XC SS C P,A D7
Add A RX C A,S, IF 5A
Execute EX RX A,S, EX 44
Add Decimal AP SS T,C P,A, D, DF FA
Halt 110 HIO SI CM 9E
Add Halfword AH RX C A,S, IF 4A
Halve (Long) HDR RRF S 24
Add Logical ALR RR C IE
Halve (Short) HER RRF S 34
Add Logical AL RX C A,S, 5E Insert Character IC RX A 43
Add Normalized Insert Storage Key ISK RRZ M, A,S 09 (Long) NADR RRF,C S,U,E,LS 2A
Load LR RR 18
Add Normalized
Load L RX A,S 58
(Long) NAD RXF,C A,S,U,E,LS 6A
Load Address LA RX 41
Add Normalized
Load and Test LTR RR C 12
( Short) NAER RRF,C S,U,E,LS 3A
Load and Test
Add Normalized
(Long) LTDR RRF,C S 22
( Short) NAE RXF,C A,S,U,E,LS 7A
Load and Test
Add Unnorm-
( Short) LTER RRF,C S 32
alized (Long) AWR RRF,C S, E,LS 2E
Load Complement LCR RR C IF 13
Add Unnorm-
Load Complement
alized (Long) AW RXF,C A,S, E,LS 6E (Long) LCDR RRF,C S 23
Add Unnorm-
Load Complement alized (Short) AUR RRF,C S, E,LS 3E ( Short) LCER RRF,C S 33
Add Unnorm-
Load Halfword LH RX A,S 48
alized (Short) AU RXF,C A,S, E,LS 7E
Load (Long) LDR RRF S 28
AND NR RR C 14 Load (Long) LD RXF A,S 68
AND N RX C A,S 54 Load Multiple LM RS A,S 98
AND NI SI C P,A 94 Load Negative LNR RR C 11
AND NC SS C P,A D4 Load Negative
Branch and Link BALR RR 05 ( Long) LNDR RRF,C S 21
Branch and Link BAL RX 45 Load Negative
Branch on ( Short) LNER RRF,C S 31
Condition BCR RR 07 Load Positive LPR RR C IF 10
Branch on Load Positive Condition BC RX 47 ( Long) LPDR RRF,C S 20 Branch on Count BCTR RR 06 Load Positive
Branch on Count BCT RX 46 (Short) LPER RRF,C S 30 Branch on Index Load PSW LPSW SI LM, A,S 82
High BXH RS 86 Load (Short) LER RRF S 38
Branch on Index Load (Short) LE RXF A,S 78
Low or Equal BXLE RS 87
Move MVI SI P,A 92 Compare CR RR C 19 Move MVC SS P,A D2
Compare C RX C A,S 59 Move Numerics MVN SS P,A Dl Compare Decimal CP SS T,C A, D F9 Move with Offset MVO SS P,A Fl
Appendix G 159
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