The sign bit of the second operand is made zero,

while characteristic and fraction are not changed. In

short-precision, the low-order half of the result register

remains unchanged and is not tested.

Resulting Condition Code:

o Result fraction is zero

1

2 Result is greater than zero

3

Program Interruptions:Operation (if floating-p@int feature is not in

sta.lled)

Specification

Load Negative

LNERRR (Short Operands)

31

7 8 11 12 15

LNDR RR (Long Operands)

21

78 1112 15

The second operand is placedin the first operand

location with the sign made minus.

The sign bit of the second operand is made one,

even if the fraction is zero. Characteristic and fraction

are not changed. In short-precision, the low-order half

of the result register remains unchanged and is not

tested.

Resulting Condition Code:

o Result fraction is zero

1 Result is less than zero

2

3

Program Interruptions:Operation (if floating-point

stalled)Specification Add Normalized AER RR. (Short Operands) I 3A R1 I R2 I 0 78 11 12 15

AE RX (Short Operands)I 7A Rl I X

2I B2 0 78 11 12 1516 1920 44

feature is not in-

D2

31

ADR RR (Long Operands)I 2A Rl I R2 I 0 78 11 12 15

AD RX (Long Operands)I 6A Rl I X

2I B2 D2 0 7 8 11 12 1516 1920 31

The second operand is added to the first operand, and

the normalized sum is placed in the first operand

location.

In short-precision the low-order halves of the float

ing-point registers are ignored and remain unchanged.

Addition of two floating-point numbers consists of a

characteristic comparison and a fraction addition. The

characteristics of the two operands are compared, and

the fraction with the smaller characteristic is right

shifted; its characteristic is increased by one for each

hexadecimal digit of shift, until the two characteristics

agree. The fractions are then added algebraically to

form an intermediate sum. If an overflow carry occurs,

the intermediate sum is right-shifted one digit, and the

characteristic is increased by one. If this increase

causes a characteristic overflow, an exponent-overflow

exception is signaled, and a program interruption

occurs.

The short intermediate sum consists of seven hex

adecimal digits and possible carry. The low-order

digit is a guard digit retained from the fraction which

is shifted right.Only one guard digit participates in

the fraction addition. The guard digit is zero if no shift

occurs. The long intermediate sum consists of 14 hex

adecimal digits and a possible carry. No guard digit

is retained.

After the addition, the intermediate sum is left

shifted as necessary to form a normalized fraction;

vacated low-order digit positions are filled with zeros

and the characteristic is reduced by the amount of

shift.

If normalization causes the characteristic to under

flow, characteristic and fraction are made zero, an

exponent-underflow exception exists, and a program

interruption occurs if the corresponding mask bit is

one. If no left shift takes place the intermediate sum

is truncated to the proper fraction length.

When the intermediate sum is zero and the signifi

cance mask bit is one, a significance exception exists,

and a program interruption takes place. No normal

ization occurs; the intermediate sum characteristic

remains unchanged. When the intermediate sum is

zero and the significance mask bit is zero, the program

while characteristic and fraction are not changed. In

short-precision, the low-order half of the result register

remains unchanged and is not tested.

Resulting Condition Code:

o Result fraction is zero

1

2 Result is greater than zero

3

Program Interruptions:

sta.lled)

Specification

Load Negative

LNER

31

7 8 11 12 15

LNDR RR (Long Operands)

21

78 1112 15

The second operand is placed

location with the sign made minus.

The sign bit of the second operand is made one,

even if the fraction is zero. Characteristic and fraction

are not changed. In short-precision, the low-order half

of the result register remains unchanged and is not

tested.

Resulting Condition Code:

o Result fraction is zero

1 Result is less than zero

2

3

Program Interruptions:

stalled)

AE RX (Short Operands)

2

feature is not in-

D2

31

ADR RR (Long Operands)

AD RX (Long Operands)

2

The second operand is added to the first operand, and

the normalized sum is placed in the first operand

location.

In short-precision the low-order halves of the float

ing-point registers are ignored and remain unchanged.

Addition of two floating-point numbers consists of a

characteristic comparison and a fraction addition. The

characteristics of the two operands are compared, and

the fraction with the smaller characteristic is right

shifted; its characteristic is increased by one for each

hexadecimal digit of shift, until the two characteristics

agree. The fractions are then added algebraically to

form an intermediate sum. If an overflow carry occurs,

the intermediate sum is right-shifted one digit, and the

characteristic is increased by one. If this increase

causes a characteristic overflow, an exponent-overflow

exception is signaled, and a program interruption

occurs.

The short intermediate sum consists of seven hex

adecimal digits and possible carry. The low-order

digit is a guard digit retained from the fraction which

is shifted right.

the fraction addition. The guard digit is zero if no shift

occurs. The long intermediate sum consists of 14 hex

adecimal digits and a possible carry. No guard digit

is retained.

After the addition, the intermediate sum is left

shifted as necessary to form a normalized fraction;

vacated low-order digit positions are filled with zeros

and the characteristic is reduced by the amount of

shift.

If normalization causes the characteristic to under

flow, characteristic and fraction are made zero, an

exponent-underflow exception exists, and a program

interruption occurs if the corresponding mask bit is

one. If no left shift takes place the intermediate sum

is truncated to the proper fraction length.

When the intermediate sum is zero and the signifi

cance mask bit is one, a significance exception exists,

and a program interruption takes place. No normal

ization occurs; the intermediate sum characteristic

remains unchanged. When the intermediate sum is

zero and the significance mask bit is zero, the program