Channel Not Operational (NXX): The addressed
channel is not operational, or the channel address in
the instruction is invalid. A channel is not operational
when it is not provided in the system or when it has
been switched to the test mode. The states of the
addressed I/O device and sub channel are not signifi­
cant.
Resetting of the Input/Output System
Two types of resetting can occur in the I/O system.
The reset states overlap the hierarchy of states distin­
guished for the purpose of responding to the CPU during the execution of I/O instructions. Resetting ter­
minates the current operation, disconnects the device
from the channel, and may place the device in cer­
tain modes of operation. The meaning of the two
reset states for each type of I/O device is specified in
the Systems Reference Library (SRL) publication for
the device.
System Re,set The system-reset function is performed when the
system-reset key is pushed, when initial program
loading is performed, or when a system power-on
sequence is completed. System reset causes the channel to terminate opera­
tions on all subchannels. Status information and in­
terruption conditions in the subchannels are reset, and
all operational subchannels are placed in the available
state. The channel sends the system-reset signal to all I/O devices attached to it.
If the device is! currently communicating over the I/O interface, the device immediately disconnects
from the channel. Data transfer and any operation
using the facilities of the control unit are immediately
terminated, and the I/O device is not necessarily posi­
tioned at the beginning of a block. Mechanical mo­
tion not involving the use of the control unit, such as
rewinding magnetic tape or positioning a disk access
mechanism, proceeds to the normal stopping point, if
possible. The device remains unavailable until the
termination of mechanical motion or the inherent
cycle of operation, if any, whereupon it becomes available" Status information in the device and con­
trol unit :is reset, and no interruption condition is gen­
erated upon completing the operation.
A control unit accessible by more than one channel
is reset if it is currently associated with a channel on
the CPU generating the reset.
Malfunction Reset
The malfunction-reset function is performed when the
channel detects equipment malfunctioning. 90 Execution of malfunction reset in the channel de­
pends on the type of error and the model. It may
cause all operations in the channel to be terminated
and all operational subchannels to be reset to the
available state. The channel may send either the mal­
function-reset signal to the device connected to the
channel at the time the malfunctioning is detected,
or channels sharing common equipment with the CPU may send the system-reset signal to all devices
attached to the channel.
When the channel signals malfunction reset over
the interface, the device immediately disconneots
from the channel. Data transfer and any operation
using the facilities of the control unit are immediately
terminated, and the I/O device is not necessarily po­
sitioned at the beginning of a block. Mechanical mo­
tion not involving the control unit, such as rewinding
magnetic tape or positioning a disk access mechanism,
proceeds to the normal stopping point, if possible.
The device remains unavailable until the termination
of mechanical motion or the inherent cycle of opera­
tion, if any, whereupon it becomes available. Status information associated with the addressed device is
reset, but an interruption condition may be generated
upon completing any mechanical operation.
When a malfunction reset occurs, the program is
alerted by an I/O interruption or, when the malfunc­
tion is detected during the execution of an I/O instruc­
tion, by the setting of the condition code. In either
case the csw identifies the condition. The device ad­
dressed by the I/O instruction or the device identified
by the I/O interruption, however, is not necessarily
the one placed in the malfunction-reset state. In chan­
nels sharing common equipment with the CPU, mal­
functioning detected by the channel may be indicated
by a machine-check interruption, in which case a csw
is not stored and a device is not identified. The
method of identifying malfunctioning depends upon
the model. Condition Code The results of certain tests by the channel and device,
and the original state of the addressed part of the I/O system are used during the execution of an I/O in­
struction to set one of four condition codes in bit
positions 34 and 35 of the psw. The condition code
is set at the time the execution of the instruction is
completed, that is, the time the CPU is released to
proceed with the next instruction. The condition code
indicates whether or not the channel has performed
the function specified by the instruction and, if not,
the reason for the rejection. The code can be used for
decision-making by subsequent branch-on-condition
operations.

The following table lists the conditions that are
identified and the corresponding condition codes for
each instruction. The states of the system and their
abbreviations are defined in "States of the Input/Out­ put System." The digits in the table represent the
numeric value of the code. The instruction START I/O can set code 0 or 1 for the AAA state, depending on
the type of operation that is initiated.
CONDITION CODE FOR START TEST HALT TEST CONDITIONS I/O I/O I/O CHAN
Available AAA 0 0 0 Interruption pend. in device AAI 0 0 Device working AAW 0 0 Device not operational AAN 3 3 0 0 Interruption pend. in sub channel AIX
For the addressed device 2 0 0 For another device 2 2 0 0 Subchannel working AWX 2 2 0 Subchannel not operational ANX 3 3 3 0 Interruption pend. in channel IXX sce note below 1 Channel working WXX 2 2 2 2 Channel not operational NXX 3 3 3 3 Error Channel equipment error P P Channel programming error Device error CSW or its status portion is stored at location 64 during
execution of the instruction.
- The condition cannot be identified during execution of the in­
struction. NOTE: For the purpose of executing START I/O, TEST I/O,
and HALT I/O, a channel containing a pending interruption
condition appears the same as an available channel, and the
condition codes for the IXX state are the same as for the AXX
state, where the X's represent the states of the subchannel and
the device. As an example, the condition eode for the IAA
state is the same as for the AAA state.
The available condition is indicated only when no
errors are detected during the execution of the I/O instruction. When a programming error occurs in the
information placed in the CAW or ccw and the ad­
dressed channel or subchannel is working, either con­
dition code 1 or 2 may be set, depending upon the
model. Similarly, either code 1 or 3 may be set when
a programming error occurs and a part of the ad­
dressed I/O system is not operational.
When a subchannel on the multiplexor channel con­
tains a pending interruption condition (state AIX),
the I/O device associated with the terminated opera­
tion normally is in the interruption-pending state.
When the channel detects during execution of TEST I/O that the device is not operational, condition code
3 is set. Similarly, condition code 3 is set when HALT I/O is addressed to a subchannel in the working state
and operating in the multiplex mode (state A WX ) ,
but the device turns out to be not operational. The
not-operational state in both situations can be caused
by operator intervention or by equipment malfunction
and, for HALT I/O, may occur when the isntruction is
addressed to a control unit other than the one cur­
rently operating.
The error conditions listed in the preceding table
include all equipment or programming errors detected
by the channel or the I/O device during execution of
the I/O instruction. Except for channel equipment er­
rors, in which case no csw may be stored, the status
portion of the csw identifies the error. Three types of
errors can occur:
Channel Equipment Error: The channel can detect
the following equipment errors during execution of START r/o, TEST I/O, and HALT r/o:
1. The device address that the channel received on
the interface during initial selection either has a
parity error or is not the same as the one the channel
sent out. Some device other than the one addressed
may be malfunctioning.
2. The unit-status byte that the channel received on
the interface during initial selection has a parity error.
3. A signal from the I/O device occurred during
initial selection at an invalid time or had invalid
duration.
4. The channel detected an error in its control
equipment.
The channel may perform the malfunction-reset
function, depending on the type of error and the
model. If a csw is stored, channel control check or
interface control check is indicated, depending on the
type of error.
Channel Programming Error: The channel can de­
tect the following programming errors during execu­
tion of START I/O: 1. Invalid ccw address in CAW 2. Invalid ccw address specification in CAW 3. Invalid storage protection key in CAW 4. Invalid CAW format
5. First ccw specifies transfer in channel
6. Invalid command code in first ccw
7. Initial data address exceeds addressing capacity
of model
8. Invalid count in first ccw
9. Invalid format of first ccw
The csw indicates program check.
Device Error: Programming or equipment crrors
detected by the device during the execution of START I/O are indicated by unit check or unit exception in
the csw. The instruction TEST I/O can cause unit check
to be generated.
The conditions responsible for unit check and unit
exception for each type of 1/0 device are detailed in
the SRL publication for the device.
[nput/Output Operations 91