Floati nSI-Poi nt Arith metic
The purpose of the floating-point instruction set is to
perform calculations using operands with a wide range
of magnitude and yielding results scaled to preserve
A floating-point number consists of a signcd ex­ ponent and a signed fraction. The quantity expressed
by this number is the product of the fraction and the
number 16 raised to the power of the exponent. The
exponent is expressed in excess 64 binary notation; the
fraction is expressed as a hexadecimal number having
a radix point to the left of the high-order digit.
To avoid unnecessary storing and loading operations
for results and operands, four floating-point registers
are provided. The floating-point instruction set pro­
vides for loading, adding, subtracting, comparing,
multiplying, dividing, and storing, as well as the sign
control of short or long operands. Short operands gen­
erally provide faster processing and require less stor­ age than long operands. On the other hand, long
operands provide greater accuracy of computation.
Operations may be either register to register or storage
to register. All floating-point instructions and registers
are part of the floating-point feature.
To preserve maximum precision, addition, subtrac­
tion, multiplication, and division are performed with
normalized results. Addition and subtraction may also
be performed with unnormalized results. Normalized
and unnormalized operands may be used in any float­ ing-point operation.
The condition code is set as a result of all sign con­ trol, add, subtract, and compare operations.
Data Format
Floating-point data occupy a fixed-length format,
which may be either a fullword short format or a
double-word long format. Both formats may be used
in main storage and in the floating-point registers. The
four floating-point registers are numbered 0, 2, 4,
and 6. Short Floating-Point Number Is I Characteristic I Fraction
o I 78 31 40 Long Floating-Point Number _________ Fr_a_c_ti_o_n ______ ____ o I 7 8 63
The first bit in either format is the sign bit (S). The
subsequent seven bit positions are occupied by the
characteristic. The fraction field may have either six
or 14 hexadecimal digits.
The entire set of floating-point instructions is avail­
able for both short and long operands. When short­
precision is specified, all operands and results are 32-
bit floating-point words, and the rightmost 32 bits of
the floating-point registers do not participate in the
operations and remain unchanged. An exception is the
product in MULTIPLY, which is a 64-bit word and oc­ cupies a full register. When long-precision is specified,
all operands and results are 64-bit floating-point words.
Although final results in short-precision have six
fraction digits, intermediate results in addition, sub­ traction, and division may extend to seven fraction
digits. Thc low-order digit of a seven-digit fraction is
called the guard digit and serves to increase the pre­ cision of the final result. Intermediate results in long­ precision do not exceed 14 fraction digits.
Number Representation
The fraction of a floating-point number is expressed in
hexadecimal digits. The radix point of the fraction is
assumed to be immediately to the left of the high­ order fraction digit. To provide the proper magnitude
for the floating-point number, the fraction is consid­
ered to be multiplied by a power of 16. The character­
istic portion, bits 1-7 of both floating-point formats, in­ dicates this power. The characteristic is treated as an
excess 64 number with a range from -64 through +63,
coresponding to the binary values 0-127.
Both positive and negative quantities have a true
fraction, the difference in sign being indicated by the
sign bit. The number is positive or negative according­
ly as the sign bit is zero or one.
The range covered by the magnitude (M) of a
normalized floating-point number is
in short preciSion 16-
65 L. M L. (1 -16-
) 16
, and
in long precision 16-
65 L. M L. (1 -16-
) 16
or approximately 2.4 . 10-
L. M L. 7.2 . 10
in either precision.
A number with zero characteristic, zero fraction, and
plus sign is called a true zero. A true zero may arise
as the result of an arithmetic operation because of the
particular magnitude of the operands. A result is
forced to be true zero when an exponent underflow
occurs or when a result fraction is zero and no pro­
gram interruption due to significance exception is
taken. When the program interruption is taken, the
true zero is not forced, and the characteristic and sign
of the result remain unchanged. Whenever a result has
a zero fraction, the exponent overflow and underflow
exceptions do not cause a program interruption. When
a divisor has a zero fraction, division is omitted, a
floating-point divide exception exists, and a program
interruption occurs. Otherwise, zero fractions and zero
characteristics participate as normal numbers in all
arithmetic operations.
The sign of a sum, difference, product, or quotient
with zero fraction is positive. The sign of a zero
fraction resulting from other operations is established
by the rules of algebra from the operand signs.
A quantity can be represented with the greatest pre­
cision by a floating-point number of given fraction
length when that number is normalized. A normalized
floating-point number has a nonzero high-order hex­
adecimal fraction digit. If one or more high-order
fraction digits are zero, the number is said to be un­
normalized. The process of normalization consists of
shifting the fraction left until the high-order hexadeci­
mal digit is nonzero and reducing the characteristic by
the number of hexadecimal digits shifted. A zero frac­
tion can not be normalized, and its associated char­
acteristic therefore remains unchanged when normal­
ization is called for.
Normalization usually takes place when the inter­
mediate arithmetic result is changed to the final result.
This function is called postnol'malization. In perform­
ing multiplication and division, the operands are
normalized prior to the arithmetic process. This func­
tion is called prenol'malization. Floating-point operations may be performed with
or without normalization. Most operations are per­
formed in only one of these two ways. Addition and
subtraction may be specified either way.
When an operation is performed without normaliza­
tion, high-order zeros in the result fraction are not
eliminated. The result mayor may not be normalized,
depending upon the original operands.
In both normalized and unnormalizcd operations,
the initial operands need not be in normalized form.
Also, intermediate fraction results are shifted right
when an overflow occurs, and the intermediate fraction
result is truncated to the final result length after the
shifting, if any.
Programming Note Since normalization applies to hexadecimal digits, the
three high-order bits of a normalized number may be
Condition Code
The results of floating-point sign-control, add, sub­
tract, and compare operations are used to set the con­
dition code. Multiplication, division, loading, and
storing leave the code unchanged. The condition code
can be used for dec i s ion -m a kin g by sub seq u e n t
branch-on-condition instructions.
The condition code can be set to reflect two types
of results for floating-point arithmetic. For most opera­
tions, the states 0, 1, or 2 indicate the content of the
result register is zero, less than zero, or greater than
zero. A zero result is indicated whenever the result
fraction is zero, including a forced zero. State 3 is used
when the exponent of the result overflows.
For comparison, the states 0, 1, or 2 indicate that the
first operand is equal, low, or high. CONDITION CODE SETTING FOR FLOATING-POINT ARITHMETIC 0 Add Normalized S/L zero
Add Unnormalized slL zero
Compare S/L equal
Load and Test S/L zero
Load Complement S/L zero
Load Negative s/L zero
Load Positive S/L zero
Normalized S/L zero
Subtract Un normalized S/L zero
Instruction format
< zero
< zero
< zero
< zero
< zero
< zero
< zero
> zero
> zero
> zero
> zero
> zero
> zero
> zero
Floating-point instructions use the following two
RR Format I Op Code R, R2
o 78 1112 15
RX Format I Op Code R, X
o 7 8 11 12 15 16 1 9 20 31
In these formats, Rl designates the address of a float­
ing-point register. The contents of this register will be
Floating-Point Arithmetic 41
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