The following is a summary of the purposes of the
pswfields: System Mask: Bits 0-7 of the psw are associated with I/O channels and external signals as specified in the
following table. When a mask bit is one, thc source
can interrupt the cpu. When a mask bit is zero, the
corresponding source can not interrupt the cpu and
interruptions remain pending.SYSTEM MASK HIT o
1
2
3
4
56 7
7
7INTERRUPTION SOURCE Multiplexor channel
Selector channel 1
Selector channel 2
Selector channel 3
Selector channel 4
Selector channel 5
Selector channel6 Timer
Interrupt key
External signalProtection Key: Bits 8-11 of the psw form the cpu
protection key. The key is matched with a storage key
whenever a result is stored. When the protection fea
ture is not implemented, bits 8-11 must be zero when
loaded and are zero when stored.
ASCII(A): When bit 12 of the psw is one, the codes
preferred for the extendedASCII code are generated
for decimal results. When psw 12 is zero, the codes
preferred for the extended binary-coded-decimal inter
change code are generated.
Machine-Check Mask (M): When psw bit 13 is one,
the machine-check interruption, machine check out
signal, and diagnostics occur upon malfunction detec
tion. When bit 13 of the psw is zero, the cpu is masked
for machine-check interruptions, and any associated
signals and diagnostic procedures do not take place.
The interruption does not remain pending.
WaitState (W): ""hen bit 14 of the psw is one, the
cpu is in the wait state. When psw bit 14 is zero, the
cpu is in the running state.Problem State (P): When bit 15 of the psw is one,
the cpu is in the problem state. When psw bit 15 is
zero, the cpu is in the supervisor state.
Interruption Code: Bits 16-31 of the psw identify
the cause of anI/O, program, supervisor call, or ex
ternal interruption. The code is zero when a machine
check interruption occurs.Use of the code for all five interruption types is shown in a table appearing
in the"Interruptions" section.
Instruction Length Code (ILC): The code in psw
bits 32 and33 indicates the length, in halfwords, of the
last-interpreted instruction when a program or super
visor-call interruption occurs. The code is unpredict
able forI/O, external, or machine-check interruptions.
Encoding of these bits is summarized in a table ap
pearing in the"Interruptions" sections. 70 Condition Code (CC): Bits 34 and 35 of the psw are
the two bits of the condition code. The condition
codes for all instructions arc summarized in a table
appearing in the"Branching" section. Program Mask: Bits 36-39 of the psw are the four
program mask bits. Each bit is associated with a program exception, as specified in the following table.
When the mask bit is one, the exception results in an
interruption. When the mask bit is zero, no interrup
tion occurs. Thesignificance mask bit also detennines
the manner in which Hoating-point addition and sub
traction are completed.PROGRAM MASK BIT PROGHAM EXCEPTION
36 Fixed-point overflow
37 Decimal overflow
38 Exponent underflow
39 Significance
Instruction Address: Bits40-63 of the psw are the in
struction address. This addressspecifies the leftmost
eight-bit byte position of the next instruction.
Multisystem Operation
Various fcatures are provided to permit communica
tion between individual systems. Messages may be
transmitted by means of a sharedI/O device, a chan
nel connector, or a shared storage unit. Signaling may
be accomplished when the direct control feature is in
stalled by WRITEDIRECT and READ DIRECI' and by the
signal-in lines of the external interruption.
The multisystem feature adds to these facilities the
ability to relocate direct addressed locations, to signal
the machine malfunction of one system to another,
and to initiate system operation from another system.
Direct Address Relocation
Addresses0-4095 can be generated without a base
address or index. This property is important when the
psw and general register contents must be preserved
and restored during program-switching. These ad
dresses further include all addresses generated by the
cpu forfixed locations, such as old PSW, new psw,
channel address word, channel status word, and timer.
This set of addresses can be relocated by means of a
mainprefix to permit more than one cpu to use one
uniquely addressed storage. Furthermore, an alternateprefix is provided to permit a change in relocation in
case storage malfunction occurs or reconfiguration be
comes otherwise desirable.
Aprefix is used whenever an address has the high
order 12 bits all-zero. The use of theprefix is inde
pendent of the manner in which the address is gener
ated and does not apply to the components, such as the
psw
following table. When a mask bit is one, thc source
can interrupt the cpu. When a mask bit is zero, the
corresponding source can not interrupt the cpu and
interruptions remain pending.
1
2
3
4
5
7
7
Selector channel 1
Selector channel 2
Selector channel 3
Selector channel 4
Selector channel 5
Selector channel
Interrupt key
External signal
protection key. The key is matched with a storage key
whenever a result is stored. When the protection fea
ture is not implemented, bits 8-11 must be zero when
loaded and are zero when stored.
ASCII(A): When bit 12 of the psw is one, the codes
preferred for the extended
for decimal results. When psw 12 is zero, the codes
preferred for the extended binary-coded-decimal inter
change code are generated.
Machine-Check Mask (M): When psw bit 13 is one,
the machine-check interruption, machine check out
signal, and diagnostics occur upon malfunction detec
tion. When bit 13 of the psw is zero, the cpu is masked
for machine-check interruptions, and any associated
signals and diagnostic procedures do not take place.
The interruption does not remain pending.
Wait
cpu is in the wait state. When psw bit 14 is zero, the
cpu is in the running state.
the cpu is in the problem state. When psw bit 15 is
zero, the cpu is in the supervisor state.
Interruption Code: Bits 16-31 of the psw identify
the cause of an
ternal interruption. The code is zero when a machine
check interruption occurs.
in the
Instruction Length Code (ILC): The code in psw
bits 32 and
last-interpreted instruction when a program or super
visor-call interruption occurs. The code is unpredict
able for
Encoding of these bits is summarized in a table ap
pearing in the
the two bits of the condition code. The condition
codes for all instructions arc summarized in a table
appearing in the
program mask bits. Each bit is associated with a pro
When the mask bit is one, the exception results in an
interruption. When the mask bit is zero, no interrup
tion occurs. The
the manner in which Hoating-point addition and sub
traction are completed.
36 Fixed-point overflow
37 Decimal overflow
38 Exponent underflow
39 Significance
Instruction Address: Bits
struction address. This address
eight-bit byte position of the next instruction.
Multisystem Operation
Various fcatures are provided to permit communica
tion between individual systems. Messages may be
transmitted by means of a shared
nel connector, or a shared storage unit. Signaling may
be accomplished when the direct control feature is in
stalled by WRITE
signal-in lines of the external interruption.
The multisystem feature adds to these facilities the
ability to relocate direct addressed locations, to signal
the machine malfunction of one system to another,
and to initiate system operation from another system.
Direct Address Relocation
Addresses
address or index. This property is important when the
psw and general register contents must be preserved
and restored during program-switching. These ad
dresses further include all addresses generated by the
cpu for
channel address word, channel status word, and timer.
This set of addresses can be relocated by means of a
main
uniquely addressed storage. Furthermore, an alternate
case storage malfunction occurs or reconfiguration be
comes otherwise desirable.
A
order 12 bits all-zero. The use of the
pendent of the manner in which the address is gener
ated and does not apply to the components, such as the