The following is a summary of the purposes of the
psw fields: System Mask: Bits 0-7 of the psw are associated with I/O channels and external signals as specified in the
following table. When a mask bit is one, thc source
can interrupt the cpu. When a mask bit is zero, the
corresponding source can not interrupt the cpu and
interruptions remain pending. SYSTEM MASK HIT o
5 6 7
7 INTERRUPTION SOURCE Multiplexor channel
Selector channel 1
Selector channel 2
Selector channel 3
Selector channel 4
Selector channel 5
Selector channel 6 Timer
Interrupt key
External signal Protection Key: Bits 8-11 of the psw form the cpu
protection key. The key is matched with a storage key
whenever a result is stored. When the protection fea­
ture is not implemented, bits 8-11 must be zero when
loaded and are zero when stored.
ASCII(A): When bit 12 of the psw is one, the codes
preferred for the extended ASCII code are generated
for decimal results. When psw 12 is zero, the codes
preferred for the extended binary-coded-decimal inter­
change code are generated.
Machine-Check Mask (M): When psw bit 13 is one,
the machine-check interruption, machine check out­
signal, and diagnostics occur upon malfunction detec­
tion. When bit 13 of the psw is zero, the cpu is masked
for machine-check interruptions, and any associated
signals and diagnostic procedures do not take place.
The interruption does not remain pending.
Wait State (W): ""hen bit 14 of the psw is one, the
cpu is in the wait state. When psw bit 14 is zero, the
cpu is in the running state. Problem State (P): When bit 15 of the psw is one,
the cpu is in the problem state. When psw bit 15 is
zero, the cpu is in the supervisor state.
Interruption Code: Bits 16-31 of the psw identify
the cause of an I/O, program, supervisor call, or ex­
ternal interruption. The code is zero when a machine­
check interruption occurs. Use of the code for all five interruption types is shown in a table appearing
in the "Interruptions" section.
Instruction Length Code (ILC): The code in psw
bits 32 and 33 indicates the length, in halfwords, of the
last-interpreted instruction when a program or super­
visor-call interruption occurs. The code is unpredict­
able for I/O, external, or machine-check interruptions.
Encoding of these bits is summarized in a table ap­
pearing in the "Interruptions" sections. 70 Condition Code (CC): Bits 34 and 35 of the psw are
the two bits of the condition code. The condition
codes for all instructions arc summarized in a table
appearing in the "Branching" section. Program Mask: Bits 36-39 of the psw are the four
program mask bits. Each bit is associated with a pro­ gram exception, as specified in the following table.
When the mask bit is one, the exception results in an
interruption. When the mask bit is zero, no interrup­
tion occurs. The significance mask bit also detennines
the manner in which Hoating-point addition and sub­
36 Fixed-point overflow
37 Decimal overflow
38 Exponent underflow
39 Significance
Instruction Address: Bits 40-63 of the psw are the in­
struction address. This address specifies the leftmost
eight-bit byte position of the next instruction.
Multisystem Operation
Various fcatures are provided to permit communica­
tion between individual systems. Messages may be
transmitted by means of a shared I/O device, a chan­
nel connector, or a shared storage unit. Signaling may
be accomplished when the direct control feature is in­
stalled by WRITE DIRECT and READ DIRECI' and by the
signal-in lines of the external interruption.
The multisystem feature adds to these facilities the
ability to relocate direct addressed locations, to signal
the machine malfunction of one system to another,
and to initiate system operation from another system.
Direct Address Relocation
Addresses 0-4095 can be generated without a base
address or index. This property is important when the
psw and general register contents must be preserved
and restored during program-switching. These ad­
dresses further include all addresses generated by the
cpu for fixed locations, such as old PSW, new psw,
channel address word, channel status word, and timer.
This set of addresses can be relocated by means of a
main prefix to permit more than one cpu to use one
uniquely addressed storage. Furthermore, an alternate prefix is provided to permit a change in relocation in
case storage malfunction occurs or reconfiguration be­
comes otherwise desirable.
A prefix is used whenever an address has the high­
order 12 bits all-zero. The use of the prefix is inde­
pendent of the manner in which the address is gener­
ated and does not apply to the components, such as the
base or index registers, from which the address is
generated. The use of the prefix applies both to ad­
dresses obtained from the program (CPU or I/O), and
to fixed addresses generated by the CPU for updating
or interruption purposes.
Both main prefix and alternate prefix occupy 12
bits. One or the other replaces the 12 high-order ad­
dress bits when these are found to be zero.
The choice of main or alternate prefix is determined
by the prefix trigger. This trigger is set during initial
program loading (IPL) and remains unchanged until
the next initial program loading occurs. Manual IPL sets the prefix trigger to the state of the prefix-select
switch on the operator. control section of the system
control panel. Electronic IPL sets the prefix trigger to
the state indicated by the signal line used. The state
of the prefix is indicated by the alternate-prefix light
on the operator intervention section of the system con­
trol panel.
The prefixes can be changed by hand within 5 min­
utes from one prewired encoding to another. The low­
order four bits of a prefix always have even parity,
and the total number of one-bits in a prefix cannot
exceed seven.
Malfunction Indication A machine check out-signal occurs whenever a ma­
chine check is recognized and the machine-check mask
bit is one. The signal has D.5-microsecond to l.O-micro­ second duration and is identical in electronic charac­
teristics to the signals on the signal-out lines of the
direct control feature.
The machine check out-signal is given during ma­
chine-check handling and has a high probability of
being issued in the presence of machine malfunction. System Initialization A main IPL in-line and an alternate IPL in-line respond
to O.5-microsecond to 1.0-microsecond pulses. Either
line, when pulsed, sets the prefix trigger to the state
indicated by its name and subsequently starts initial
program loading. Thus, these lines permit electronic
initiation of IPL. The definition of the signal to which these lines re­
spond is identical in electronic characteristic to the
definition for the signal-in lines of the external inter­
Instruction format
Status-switching instructions use the following two
RR Format I Op Code Rl R2 I 0 78 11 12 15
51 Format Op Code 12 Bl Dl
78 1516 1920 31
In the RR format, the Rl field specifies a general reg­
ister, except for SUPERVISOR CALL. The R2 field speci­
fies a general register in SET STORAGE KEY and INSERT STORAGE KEY. The Rl and R2 fields in SUPERVISOR CALL
contain an identification code. In SET PROGRAM MASK the R2 field is ignored.
In the SI format the eight-bit immediate field (12)
of the instruction contains an identification code. The h field is ignored in LOAD psw and SET SYSTEM MASK. The content of the general register specified by Bl is
added to the content of the Dl field to form an address
designating the location of an operand in storage. Only one operand location is required in status-switch­
ing operations.
A zero in the Bl field indicates the absence of the
corresponding address component.
The status-switching instructions and their mnemonics,
formats, and operation codes follow. The table also
indicates the feature to which an instruction belongs
and the exceptions that cause a program interruption.
NAME MNEMONIC TYPE EXCEPTIONS CODE Load PSW LPSW SI L M, A,S 82 Set Program Mask SPM RR L 04 Set System Mask SSM SI M, A 80 Supervisor Call SVC RR OA Set Storage Key SSK RR Z M, A,S 08 Insert Storage Key ISK RR Z M, A,S 09 Write Direct WRD SI Y M, A 84
Read Direct RDD SI Y M,P,A 85
Diagnose SI M, A,S 83 NOTES A Addressing exception
L New condition codc loaded
M Privileged-operation exception P Protection exception S Specification exception
Y Direct control feature Z Protection feature
Programming Note
The program status is also switched by interruptions,
initial program loading, and manual control. Status Switching 71
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