running state may be achieved by the privileged in­
struction LOAD psw, by an interruption such as for SUPERVISOR CALL, or by initial program loading. Switch­
ing from the wait state may be achieved by an I/O or
external interruption or, again, by initial program
loading. The new psw may introduce the wait or run­
ning state regardless of the preceding state. No ex­
plicit operator control is provided for changing the
wait state.
Timer updating is not affected by the choice be­
tween running and wait state.
Programming Note
To leave the wait state without manual intervention,
the CPU should remain interruptable for some active I/O or external interruption source.
Masked States
The CPU may be masked or interruptable for all sys­
tems and machine-check interruptions and for some
program interruptions. When the CPU is interruptable
for a class of interruptions, these interruptions are
accepted. When the CPU is masked, the system inter­
ruptions remain pending, while the program and ma­
chine-check interruptions are ignored.
The system mask bits (psw bits 0-7), the program
mask bits (psw bits 36-39), and the machine-check
mask bit (psw bit 13) indicate as a group the masked
state of the CPU. When a mask bit is one, the CPU is
interruptible for the corresponding interruptions.
When the mask bit is zero, these interruptions are
masked off. The system mask bits indicate the masked
state of the CPU for the multiplexor channel, the six
selector channels, and the external signals. The pro­
gram mask bits indicate the masked state for four of
the 15 types of program exceptions. The machine­
check mask bit pertains to all machine checks. Pro­ gram interruptions not maskable, as well as the super­
visor-call interruption, are always taken. The masked
states are not indicated on the operator sections of the
system control panel.
"Most mask bits do not affect the execution of CPU operations. The only exception is the significance mask
bit, which determines the manner in which a Hoating­
point operation is completed when a significance ex­
ception occurs.
The interruptable state of the CPU is switched by
changing the mask bits in the psw. The program mask
may be changed separately by SET PROGRAM MASK, and
the system mask may be changed separately by the
privileged instruction SET SYSTEM MASK. The machine­
check mask bit can be changed only by introducing an
entire new PSW, as is the case with the problem-state
and wait-state bits. Thus, a change in the entire
masked status may be achieved by the privileged in­
struction LOAD psw, by an interruption such as for sup­ ERVISOR CALL, or by initial program loading. The new
psw may introduce a new masked state regardless of
the preceding state. No explicit operator control is
provided for changing the masked state.
Timer updating is not affected by the choice be­
tween masked or interruptable states.
Programming Note
To prevent an interruption-handling routine from be­ ing interrupted before necessary housekeeping steps
are performed, the new psw for that interruption
should mask the CPU for further interruptions of the
kind that caused the interruption.
Stopped State
When the CPU is in the stopped state, instructions and
interruptions are not executed. In the operating state,
the CPU executes instructions (if not waiting) and in­
telTui1tions (if not masked off).
The stopped state is indicated on the operator con­
trol section of the system control panel by the manual
light. The stopped state is not identified by a bit in
the psw.
A change in the stopped or operating state can be
effected only by manual intervention or by machine
malfunction. No instructions or interruptions can stop
or start the CPU. The CPU is commanded to stop when
the stop key on the operator intervention section of
the system control panel is pressed, when an address
comparison indicates equality, and when the rate
switch is set to INSTRUCTION STEP. In addition, the CPU is placed in the stopped state after power is turned on
or following a system reset, except during initial pro­
gram loading. The CPU is placed in the operating state
when the start key on the operator intervention panel
is pressed. The CPU is also placed in the operating
state when initial program loading is commenced.
The transition from operating to stopped state oc­
curs at the end of instruction execution and prior to
starting the next instruction execution. When the CPU is in the wait state, the transition takes place immedi­
ately. All interruptions pending and not masked off
are taken while the CPU is still in the operating state.
They cause an old psw to be stored and a new psw to
be fetched before entering the stopped state. Once the CPU is in the stopped state, interruptions are no longer
takcn but remain pending.
The timer is not updated in the stopped state.
Programming Notes
Except for timing considerations, execution of a pro­
gram is not affected by stopping the CPU.
When because of machine malfunction the CPU is
unable to end an instruction, the stop key is not effect­
ive, and initial program loading or system reset should
be used.
Input/output operations continue to completion
while the CPU is in the problem, wait, masked, or
stopped state. However, no new I/O operations can be
initiated while the CPU is stopped, waiting, or in the
problem state. Also, the interruption caused by I/O completion remains pending when masked off or when
the CPU is in the stopped state.
Storage Protection Storage protection is provided to protect the contents
of certain areas of storage from destruction caused by
erroneous storing of information during the execution
of a program. This protection is achieved by identify­
ing blocks of storage with a storage key and compar­
ing this key with a protection key supplied with the
data to be stored. The detection of a mismatch is a
protection exception and results in a program inter­
Area Identification
For protection purposes, main storage is divided into
blocks of 2,048 bytes, each block having an address
that is a multiple of 2,048. A four-bit storage key is
associated with each block. When data are stored in a
storage block, the storage key is compared with the
protection key. The protection key of the current psw
is used as the comparand when storing is specified by
an instruction. When storing is specified by a channel
operation, the protection key supplied to the channel
by the command address word is used as the com­
parand. The keys are said to match when they are
equal or when either one is zero.
The storage key is not part of addressable storage.
The key is changed by SET STORAGE KEY and is in­
spected by INSERT STORAGE KEY. The protection key in
the psw occupies bits 8-11 of that control word. The
protcction key of a channel is recorded in bits 0-3 of
the channel status word, which is stored as a result of
the channel operation.
Protection Action
The storage-protection system is always active. It is
independent of the problem, supervisor, or masked
state of the CPU and of the type of instruction or I/O command being executed.
When an instruction causes a protection mismatch,
execution of the instruction is suppressed or termi­
nated, and program execution is altered by a program
interruption. The protected storage location always
remains unchanged.
In general, the detection of a protected location
causes the instruction specifying this location to be
suppressed, that is to be omitted entirely. In opera­
tions using multiple words or variable-length fields,
part of the operation may already have been com­
pleted when the protected area is referenced. In these
operations the instruction cannot be suppressed and,
hence, is terminated. Protection mismatch due to an I/O operation causes
data transmission to be terminated in such a way that
the protected storage location remains unchanged.
The mismatch is indicated in the channel status word
stored as a result of the operation. Storage protection is optional in some models. When
protection is not installed, the protection key in the
psw and the protection key of the channels must be
zero; otherwise, a program interruption or program­
check I/O termination occurs.
Locations Protected
All main-storage locations where information is stored
in the course of an operation are subject to protection.
A location not actually used does not cause protection
Locations whose addresses are generated by the CPU for updating or interruption purposes, such as the
timer, channel status word, or psw addresses, are not
protected. However, when the program specifies these
locations, they are subject to protection.
Program Status Word
The psw contains all information not contained in
storage or registers but required for proper program
execution. By storing the PSW, the program can pre­
serve the detailed status of the CPU for subsequent in­ spection. By loading a new psw or part of a PSW, the
state of the CPU may be changed.
In certain circumstances all of the psw is . . _ .0d or
loaded; in others, only part of it. The entire psw is
stored, and a new psw is introduced when the CPU is
interrupted. The rightmost 32 bits are stored in BRANCH AND LINK. The LOAD PSW introduces a new PSW; SET PROGRAM mask introduces a new condition
code and program-mask field in the psw; SET SYSTEM MASK introduces a new system-mask field.
The psw has the following format: Program Status Word
System Mask Interrupti on Code 31 Instruction Address
32 33 34 35 36 39 40 63 Status Switching 69
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