0-7 System mask
o Multiplexor channel mask
1 Selector c:hannel 1 mask
2 Selector c:hannel 2 mask
3 Selector channel 3 mask
4 Selector c:hannel 4 mask
5 Selector c:hannel 5 mask
6 Selector c:hannel 6 mask
7 External mask
8-11 Protection key
12 ASCII mode (A)
13 Machine check mask (M)
14 Wait state (W)
15 Problem state (P)
16-31 Interruption code
32-33 Instruction Length code (ILC) 34-35 Condition code (CC)
36-39 Program mask
36 Fixed-point overflow mask
37 Decimal overflow mask
38 Exponent underflow mask
39 Significance mask 40-63 Instruction address
Figure 14. Program Status Word Format The interruption system permits the CPU to change
state as a result of conditions external to the system,
in input/output (I/O) units or in the CPU itself. Five
classes of interruption conditions are possible: I/O, program, supervisor call, external, and machine check.
Each class has two related psw's called "old" and "new" in unique main-storage locations (Figure 15).
In all classes, an interruption involves merely storing
the current psw in its "old" position and making the
psw at the "new" position the current psw. The "old" psw holds all necessary status information of the sys­ tem existing at the time of the interruption. If, at the
conclusion of the interruption routine, there is an in­ struction to make the old psw the current psw, the
system is lrestored to the state prior to the interruption
and the interrupted routine continues.
Address length Purpose
o 0000 0000 double word Initial program loading PSW 8 0000 1000 double word Initial program loading CCWI 16 0001 0000 double word Initial program loading CCW2 24 0001 1000 double word External old PSW 32 0010 0000 double word Supervisor call old PSW 40 0010 1000 double word Program old PSW 48 0011 0000 double word Machine check old PSW 56 0011 1000 double word Input/output old PSW 64 0100 0000 double word Channel status word
72 0100 1000 word Channel address word
76 0100 1100 word Unused 80 0101 0000 word Timer
84 0101 0100 word Unused
88 0101 1000 double word External new PSW 96 0110 0000 double word Supervisor call new PSW 1 04 011 a 1000 double word Program new PSW 112 0111 0000 double word Machine check new PSW 120 0111 1000 double word Input/output new PSW 128 1000 0000 Diagnostic scan-out area *
* The size of j,he diagnostic scan-out area depends upon the
particular system's CPU and I/O channels. Figure 15. Permanent Storage Assignments
Interruptions are taken only when the CPU is inter­
ruptable for the interruption source. The system mask,
program mask, and machine check mask bits in the
psw may be used to mask certain interruptions. When
masked off, an interruption either remains pending or
is ignored. The system mask may keep I/O and ex­ ternal interruptions pending, the program mask may
cause four of the 15 program interruptions to be ig­ nored, and the machine-check mask may cause ma­ chine-check interruptions to be ignored. Other inter­ ruptions cannot be masked off.
An interruption always takes place after one in­ struction execution is finished and before a new in­ struction execution is started. However, the occurence
of an interruption may affect the execution of the cur­ rent instruction. To permit proper programmed action
following an interruption, the cause of the interrupt­
ion is identified and provision is made to locate the
last executed instruction. Input /OutPIJt Interruption
An I/O interruption provides a means by which the CPU responds to conditions in the channels and I/O units.
An I/O interruption can occur only when the related
channel is not masked. The address of the channel
and I/O unit involved are recorded in the old psw.
Further information concerning the I/O action is pre­ served in the channel status word (csw) that is stored
during the interruption.
Program Interruption
Unusual conditions encountered in a program create
program interruptions. These conditions include in­ correct operands and operand specifications, as well
as exceptional results. The interruption code identifies
the interruption cause. Figure 16 shows the different
causes that may occur.
Interruption Program Interrupti on
Code Cause
1 00000001 Operation
2 00000010 Privileged operation
3 00000011 Execute
4 00000100 Protection 5 00000101 Addressing
6 00000110 Specification
7 00000111 Date
8 00001000 Fixed-point overflow
9 00001001 Fixed-point divide 10 00001010 Decimal overflow
11 0000101 I Decimal divide
12 00001100 Exponent overflow
13 000011 01 Exponent underflow
14 00001 110 Significance
15 00001111 Floating-point divide
Figure 16. Interruption Code for Program Interruption
Supervisor-Call Interruption
This interruption occurs as a result of execution of the
instruction SUPERVISOR CALL. Eight bits from the in­
struction format are placed in the interruption code
of the old psw, permitting a message to be associated
with the interruptions. A major use for the instruction SUPERVISOR CALL is to switch from the problem-state
to the supervisor state. This interruption may also be
used for other modes of status-switching.
External Interruption
The external interruption provides the means by
which the CPU responds to signals from the interrup­
tion key on the system control panel, the timer, and
the external signals of the direct control feature
(Figure 17). Interruption External
Code Bit I nterrupti on Cause Mask Bit
24 Timer
25 Interrupt key 7
26 External signal 6 7
27 External signal 5 7
28 External signal 4 7
29 External signal 3 7 30 External signal 2 7 3'1 External signal 1 7
Figure 17. Interruption Code for External Interruption
An external interruption can occur only when the
system mask bit 7 is one.
The source of the interruption is identified by the
interruption code in bits 24-31 of the psw. Bits 16-23
of the interruption code are made zero.
Machine-Check Interruption
The occurence of a machine check (if not masked
off) terminates the current instruction, initiates a diag­
nostic procedure, and subsequently causes the ma­
chine-check interruption. A machine check cannot be
caused by invalid data or instructions. The diagnostic
scan is performed into the scan area starting at lo­
cation 128. Proper execution of these steps depends
on the nature of the machine check.
Priority of Interruptions
During execution of an instruction, several interrup­
tion requests may occur simultaneously. Simultaneous
interruption requests are honored in the following pre­
determined order:
Machine Check Program or Supervisor Call
External Input/Output The program and supervisor-call interruptions are
mutually exclusive and cannot occur at the same time.
When more than one interruption cause requests
service, the action consists of storing the old psw and
fetching the new psw belonging to the interruption
which is taken first. This new psw subsequently is
stored without any instruction execution and the next
interruption psw is fetched. This process continues
until no more interruptions are to be serviced. When
the last interruption request has been serviced, in­
struction execution is resumed using the psw last
fetched. The order of execution of the interruption
subroutines is, therefore, the reverse of the order in
which the psw's are fetched.
Thus, the most important interruptions - I/O, ex­
ternal, program or supervisor call -are actually serv­
iced first. Machine check, when it occurs, does not al­
low any other interruptions to be taken.
Program States Over-all CPU status is determined by four types of pro­
gram-state alternatives, each of which can be changed
independently to its opposite and most of which are
indicated by a bit or bits in the psw. The program­
state alternatives are named stopped or operating,
running or waiting, masked or interruptable, and sup­
ervisor or problem state. These states differ in the way
they affect the CPU functions and the manner in which
their status is indicated and switched. All program
states are independent of each other in their functions,
indication, and status-switching. Stopped or Operating States: The stopped state is
entered and left by manual procedure. Instructions are
not executed, interruptions are not accepted, and the
timer is not updated. In the operating state, the CPU is capable of executing instructions and being inter­
Running or Waiting State: In the running state, in­
struction fetching execution proceeds in the normal
manner. The wait state is normally entered by the
program to await an interruption, for example, an I/O interruption or operator intervention from the console.
In the wait state, no instructions are processed, the
timer is updated, and 110 and external interruptions
are accepted, unless masked. Running or waiting state
is determined by the setting of bit 14 in the psw. Masked or Interruptable State: The CPU may be in­
terruptable or masked for the system, program, and
machine interruptions. \Vhen the CPU is interruptable
for a class of interruptions, these interruptions are ac­
cepted. When the CPU is masked, the system inter­
ruptions remain pending, while the program and ma­
chine-check interruptions are ignored. The interrupt­
able states of the CPU are changed by changing the
mask bits of the psw.
System Structure 17
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