I nterru ptions
The interruption system permits the CPU to change its
state as a result of conditions external to the system,
in I/O units, or in the CPU itself. The five classes of
these conditions are input; output, program, super­
visor-call, external, and machine-check interruptions.
Interruption Action An interruption consists of storing the current psw as
an old psw and fetching a new psw.
Processing resumes in the state indicated by the
new psw. The old psw contains the address of the in­
struction that would have been executed next if an
interruption had not occurred and the instruction­
length code of the last-interpreted instruction.
Interruptions are taken only when the CPU is inter­
ruptable for the interruption source. Input/output and
external interruptions may be masked by the system
mask, four of the 15 program interruptions may be
masked by the program mask, and the machine-check
interruptions may be masked by the machine-check
mask.
An interruption always takes place after one instruc­
tion interpretation is finished and before a new in­
struction interpretation is started. However, the oc­
currence of an interruption may affect the execution
of the current instruction. To permit proper program­
med action following an interruption, the cause of the
interruption is identified and provision is made to
locate the last-interpreted instruction.
When the CPU is commanded to stop, the current
instruction is finished, and all interruptions that are
pending or become pending before the end of the
instruction, and which are not masked, are taken.
The details of instruction execution, source identifi­
cation, and location determination are explained in
later sections and are summarized in the following
table.
Programming Note
A pending interruption will be taken even if the CPU becomes interruptable during only one instruction.
76 INSTRUC­ TION INTERRUPTION SOURCE JDENTlFICA TlON INTERRUPTION CODE MASK ILC EXE- PSW BITS 16-31 BITS SET CUTION Input/Output (old PSW 56, new PSW 120, priority 4)
Multiplcxor channel 00000000 aaaaaaaa 0 x complete Scledor channell 00000001 aaaaaaaa 1 x complcte Scledor channel 2 00000010 aaaaaaaa 2 x complete
Selector channel 3 00000011 aaaaaaaa 3 x complete Seledor channel 4 00000100 aaaaaaaa 4 x complete Selector channel 5 00000101 aaaaaaaa 5 x complete Scledor channel 6 00000110 aaaaaaaa 6 x completc Program (old PSW 40, new PSW 104, priority 2) Operation 0000000000000001 1,2,3
Privileged opcration 0000000000000010 1,2
Executc 0000000000000011 2 Protcction 0000000000000100 0,2,3 Addressing 00000000 00000101 1,2,3 Specification 00000000 00000110 1,2,3
Data 00000000 00000111 2,3
Fixed-point overflow 00000000 00001000 36 1,2
Fixcd-point divide 00000000 00001001 1,2
Dccimal overflow 00000000 00001010 37 3
Decimal divide 0000000000001011 3
Exponent overflow 00000000 00001100 1,2
Exponcnt underflow 00000000 000011 0 1 38 1,2 Significance 0000000000001110 39 1,2
Floating-point divide 0000000000001111 1,2
supprcss
supprcss
suppress
suppress/
terminate
suppress/
terminate
suppress
terminate
complete
suppress/
complete
complete
suppress
terminate
complcte
complete
suppress Supel'visol' Call (old PSW 32, new PSW 96, priority 2)
Instruction bits 00000000 r rr r r 1'1' r 1 complete External (old PSW 24, new PSW 88, priority 3 )
Extcrnal signal 1 00000000 xxxxxxx 1 7 x complete
External signal 2 00000000 xxxxxx1x 7 x complete
External signal 3 00000000 xxxxx lxx 7 x complete
External signal 4 00000000 xxxxlxxx 7 x complete
External signal 5 00000000 xxxlxxxx 7 x complete
External signal 6 00000000 xxlxxxxx 7 x complete
Interrupt key 00000000 xlxxxxxx 7 x complete
Timcr 00000000 lxxxxxxx 7 x complete
Machine Check (old PSW 48, new PSW 112, priority 1)
Machine malfunction 00000000 00000000 13 x terminate NOTES a Device address bits
r Bits of R, and R2 field of SUPERVIson CALL
x Unpredictable

Instruction Execution
An interruption occurs when the preceding instruction
is finished and the next instruction is not yet started.
The manner in which the preceding instruction is
finishcd may be influenced by the cause of the inter­
ruption. The instruction is said to have been com­
pleted, terminated, or suppressed.
In the case of instruction completion, results are
stored and the condition code is set as for normal in­
struction operation, although the result may be influ­
enced by the exception which has occurred.
In the case of instruction termination, all, part, or
none of the result may be stored. Therefore, the result
data are unpredictable. The setting of the condition
code, if called for, may also be unpredictable. In
general, the results should not be used for further
computation.
In the case of instruction suppression, the execution
proceeds as if no operation were specified. Results
are not stored, and the condition code is not changed.
Source Identification
The five classes of interruptions are distinguished by
the storage locations in which the old psw is stored
and from which the new psw is fetched. The detailed
causes are further distinguishcd by the interruption
code of the old psw, except for the machine-check
interruption. The bits of the interruption code are
numbered 16-31, according to their position in the psw.
For 110 interruptions, additional information is pro­
vided by the contents of the channel status word
stored as part of the 110 interruption.
For machine-check interruptions, additional infor­
mation is provided by the diagnostic procedure, which
is part of the interruption.
The following table lists the permanently allocated
main-storage locations. ADDRESS LENGTH PURPOSE a 0000 0000 Double word Initial program loading PSW 8 0000 1000 Double word Initial program loading CCW1
16 00010000 Double word Initial program loading CCW2
24 0001 1000 Double word External old PSW 32 0010 0000 Double word Supervisor call old PSW 40 0010 1000 Double word Program old PSW 48 0011 0000 Double word Machine old PSW 56 00111000 Double word Input/output old PSW 64 0100 0000 Double word Channel status word
72 0100 1000 Word Channc1 address word
76 0100 1100 Word Unused 80 0101 0000 Word Timer
84 0101 0100 Word Unused
88 0101 1000 Double word External new PSW 96 0110 0000 Double word Supervisor call new PSW 104 0110 1000 Double word Program new PSW 112 0111 0000 Double word Machine-check new PSW 120 0111 1000 Double word Input/output new PSVV 128 1000 0000 Diagnostic scan-out areal) I)Thc size of the diagnostic scan-out mea depends on the par-
ticular model and I/O channels.
Location Determination
For some interruptions, it is desirable to locate the in­
struction being interpreted when the interruption oc­
curred. Since the instruction address in the old psw
designates the instruction to be executed next, it is
necessary to know the lcngth of the preceding instruc­
tion. This length is recorded in bit positions 32 and
33 of the psw as the instruction-length code.
The instruction-length code is predictable only for
program and supervisor-call interruptions. For I/O
and external interruptions, the interruption is not
caused by the last-interpreted instruction, and the
code is not predictable for these instructions. For
machine-check interruptions, the setting of the code
may be affected by the malfunction and, therefore, is
unpredictable.
For the supervisor-caB interruption, the instruction­
length code is 1, indicating the halfword length of SUPERVISOR CALL. For program interruptions, the codes
1, 2, and 3 indicate the instruction length in halfwords.
The code 0 is reserved for program interruptions
where the length of the instruction is not available be­
cause of certain overlapping conditions in struction
fetching. In code-O cases, the instruction address in
the old psw does not represent the next instruction
address. Instruction-length code 0 can occur for a
program interruption only when the interruption is
caused by a protected or an unavailable data address.
The following table shows the states of the instruction­
length code. INSTRUC- TION INSTRUC- INSTRUC- J.ENGTH psw BITS TJON INsTRUCTION TION CODE 32-33 BITS 0-1 LENGTH FORMAT a 00 Not available
1 01 00 One halfword RR
2 10 01 Two halfwords RX
2 10 10 Two halfwords RS or SI 3 11 11 Three halfwords SS Programming Notes
When a program interruption is due to an incorrect
branch address, the location determined from the in­
struction address and instruction-length code is the
branch address and not the location of the branch
instruction.
When an interruption occurs while the CPU is in the
wait state, the instruction-length code is always unpre­
dictable.
The instruction EXECUTE represents upon interrup­
tion an instruction-length code which docs not reflect
thc length of the instruction executed, but is 2, the
length of EXECUTES.
Interruptions 77