Termination of the I/O operation normally is indi­
cated by two conditions: channel end and device end.
The channel-end condition indicates that the I/O de­
vice has received or provided all information associ­
ated with the operation and no longer needs channel
facilities. The device-end signal indicates that the I/O device has terminated execution of the operation.
The device-end condition can occur concurrently with
the channel-end condition or later. Operations that tie up the control unit after releasing
channel facilities may, under certain conditions, cause
a third type of signal. This signal, called control unit
end, may occur only after channel end and indicates
that the control unit is available for initiation of an­
other operation.
The conditions signaling the termination of an I/O operation can be brought to the attention of the pro­
gram by I/O interruptions or, when the channel is
masked, by programmed interrogation of the I/O de­
vice. In either case, these conditions cause storing the
csw, which contains additional information concern­
ing the execution of the operation. At the time the
channel-end condition is generated, the channel pro­
vides an address and a count that indicate the extent
of main storage used. Both the channel and the device
can provide indications of unusual conditions. The
device-end and control-unit-end conditions can be ac­
companied by error indications from the device.
Facilities are provided for the program to initiate
execution of a chain of commands with a single START I/O. When command chaining is specified, the receipt
of the device-end signal causes the channel to fetch
a new ccw and to initiate a new command at the
device. A chained command is initiated by mcans of
the same sequence of signals over the I/O interface as
the first command specified by START I/O. The condi­
tions signaling the termination of an operation are
not made available to the program when command
chaining occurs.
Conditions that initiate I/O interruptions are asyn­
chronous to the activity in the CPU, and more than one
condition can occur at the same time. The channel and
the CPU establish priority among the conditions so that
only one interruption request is processed at a time.
The conditions are preserved in the I/O devices and
subchannels until accepted by the CPU. Execution of an I/O operation or chain of operations
thus involves up to four levels of participation. Except
for the effects of shared equipment, the CPU is tied up
for the duration of execution of START I/O, which
lasts at most until the addressed I/O device responds
to the first command. The subchannel is busy with the
execution from the time the operation is initiated at
the I/O device until the channel-end condition for the
last operation of the command chain is accepted by
thc CPU. The control unit may remain busy after the
subchannel has been released and may generate the
control-unit-end condition when it becomes free. Final­
ly, the I/O device is busy from the initiation of the
first command until the device-end condition associ­
ated with the last operation is cleared. A pending
device-end condition causes the associated device to
appear busy, but does not affect the state of any other
part of the system. A pending control unit end blocks
communications through the control unit to any device
attached to it, while a pending channel end normally
blocks all communications through the subchannel. Compatibility of Operation
The organization of the I/O system provides for a uni­
form method of controlling I/O operations. The capac­
ity of a channel, however, depends on its use and on
the model to which it belongs. Channels are provided
with different data-transfer capabilities, and an I/O device designed to transfer data only at a specific rate
(a magnetic tape unit or a disk storage for example)
can operate only on a channel that can accommodate
at least this data rate.
The data rate a channel can accommodate depends
also on the way the I/O operation is programmed. The
channel can sustain its highest data rate when no data
chaining is specified. Data chaining reduces the maxi­
mum allowable rate, and the extent of the reduction
depcnds on the frequency at which new ccw's are
fetched and on the address resolution of the first byte
in the new area. Furthermore, since the channel may
share main storage with the CPU and other channels,
activity in the rest of the system affects the accessi­
bility of main storage and, hence, the instantaneous
load the channel can sustain.
In view of the dependence of channel capacity on
programming and on activity in the rest of the system,
an evaluation of the ability of a specific I/O configu­
ration to function concurrently must be based on a
consideration of both the data rate and the way the I/O operations are programmed. Two systems employ­
ing identical complements of I/O devices may be able
to executc certain programs in common, but it is pos­
sible that other programs requiring, for example, data
chaining, may not run on one of the systems.
Control of Input/Output Devices
The CPU controls I/O operations by means of four I/O instructions: START I/O, TEST I/O, HALT I/O, and TEST CHANNEL.
The instruction TEST CHANNEL addresscs a channel;
it does not address an I/O device. The other three I/O instructions address a channel and a device on that
channel. Input/Output Device Addressing
An I/O device is designated by an I/O address. Each I/O address corresponds to a unique I/O device and is
specified by means of an II-bit binary number in the I/O instruction. The address identifies, for example, a
particular magnetic tape drive, disk access mcchanism,
or transmission line.
The I/O address consists of two parts: channel ad­
dress in the three high-order bit positions, and a device
address in the eight low-order bit positions. The chan­
nel address specifies the channel to which the instruc­
tion applies; the device address identifies the particular I/O device in that channel. Any number in the range 0-255 can be used as a device address, providing facili­
ties for addressing 256 devices per channel. The assign­
ment of I/O addresses is:
ADDRESS 000 xxxx xxxx 001 xxxx xxxx 010 xxx x xxxx 011. xxxx xxxx
1. 00 xxxx xxxx 101 xxx x xxxx
11 0 xxxx xxxx
111 xxxx xxxx
Devices on the multiplexor channel
Devices on selector channel 1
Devices on selector channel 2
Devices on selector channel 3
Devices on selector channel 4
Devices on selector channel 5
Devices on selector channel 6
Invalid On the multiplexor channel the device address
identifies the su bchannel as well as the I/O device. A
subchannel can be assigned a unique device address,
or it can be referred to by a group of addresses. When
more than one device address 'designates the same sub­
channel, the subchannel is called shared.
The following table lists the basic assignment of de­
vice addresses on the multiplexor channel. Addresses
with a zero in the high-order bit position pertain to
subchannels that are not shared. The seven low-order
bit positions of an address in this set identify one of
128 distinct subchannels. The presence of a one in the
high-order bit position of the address indicates that
the address refers to a shared sub channel. There are
eight such shared subchannels, each of which may be
shared by as many as 16 I/O devices. In addresses that
designate shared subchannels, the four low-order bit
positions identify the I/O device on the subchannel. ADDRESS 00000000 to 0111 1111 1000 xxxx 1001 xxxx 1.010 xxxx 1011 xxxx 1100 xxxx 1101. xxxx 1110 xxxx
1111 xxxx ASSIGNMENT Devices that do not share a subchannel
Devices on shared subchanncl 0 Devices on shared subchannel 1
Devices on shared subchanncl 2
Devices on shared subchannel 3
Devices on shared subchannel 4
Devices on shared subchannel 5
Devices on shared subchanncl 6
Devices on shared subchannel 7 Physically, the shared subchannels are the same as
the first eight non-shared subchannels. In particular,
the set of addresses 1000 xxxx refers to the same sub­
channel as the address 00000000, the set 1001 xxxx re­
fers to the same sub channel as the address 0000 0001, etc, while the set 1111 xxxx refers to the same subchan­
nel as the address 00000111. Thus, the installation of
all eight sets of devices on the shared subchannels re­
duces the maximum possible number of devices that
do not share a subchannel to 120. For devices sharing a control unit (for example,
magnetic tape units and the 2702 Transmission Con­ trol), the high-order bit positions of the device address
identify the control unit. The number of bit positions
in the common field depends upon the number of de­
vices installed but is designed to accommodate 16 or
the high-order bits of all addresses are common. Con­ trol units with more than 16 devices may be assigned
noncontiguous sets of 16 addresses. The low-order bit
positions of the address identify the device on the con­
trol unit.
When the control unit is designed to accommodate
fewer devices than can be addressed with the common
field, the control unit does not recognize the addresses
not assigned to it. For example, if a control unit is
designed to control devices having only bits 0000-1001 in the low-order positions, it does not recognize ad­
dresses containing 1010-1111 in these bit positions.
However, when a contra] unit has fewer than 16 de­
vices installed but is designed to accommodate 1 or
more, it may respond to all 16 addresses and may in­
dicate unit check for the invalid addresses.
Devices sharing both a control unit and a subchan­
nel ( magnetic tape units, disk access mechanism)
are always assigned as sets of 16 addresses, with four
high-order bits common. These addresses refer to the
same sub channel even if the control unit does not
recognize the whole set.
Input! output devices accessible through more than
one channel have a distinct address for each path of
communications. This address identifies the channel,
sub channel, and the control unit. For devices sharing
a control unit, the position of the address identifying
Input/Output Operations 87
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