Programming Note
Control operations for which the entire operation is specified in the command code may be executed as
immediate operations. Whether the control function is
executed as an immediate operation depends on the
operation and type of device and is specified in the SRL publication for the device.
Termination of Data Transfer
When the device accepts a command, the subchannel
is set up for data transfer. The subchannel is said to
be working during this period. Unless the channel de­
tects equipment malfunctioning or, on the selector
channel, the operation is terminated by HALT I/O, the
working state lasts until the channel receives the chan­
nel-end signal from the device. When no command
chaining is specified or when chaining is suppressed
because of unusual conditions, the channel-end con­
dition causes the operation at the subchannel to be ter­
minated and an interruption condition to be generated.
The status bits in the associated csw indicate channel
end and the unusual conditions, if any. The device can
signal channel end at any time after initiation of the
operation, and the signal may occur before any data
have been transferred.
For operations not involving data transfer, the de­
vice normally controls the timing of the channel-end
condition. The duration of data transfer operations
may be variable and may be controlled by the device
or the channel.
Excluding equipment errors and HALT I/O, the chan­
nel signals the device to terminate data transfer when­
ever any of the following conditions occurs:
The storage areas specified for the operation are
exhausted or filled. Program-check condition is detected.
Protection-check condition is detected.
Chaining-check condition is detected.
The first of these conditions occurs when the channel
has stepped the count in the last ccw associated with
the operation to zero. A count of zero indicates that
the channel has transferred all information specified by the program. The other three conditions are due to
errors and cause premature termination of data trans­
fer. In either case, the termination is signaled in re­
sponse to a service request from the device and causes
data transfer to cease. If the device has no blocks de­ fined for the operation (such as writing on magnetic
tape), it terminates the operation and generates the
channel-end condition.
The device can control the duration of an operation
and the timing of channel end by blocking of data. On certain operations for which blocks are defined (such
as reading on magnetic tape), the device does not
provide the channel-end signal until the end of the
block is reached, regardless of whether or not the de­
vice has been previously signaled to terminate data
The channel suppresses initiation of an I/O operation
when the data address in the first ccw associated with
the operation exceeds the addressing capacity of the
model. Complete check for the validity of the data ad­
dress is performed only as data are transferred to or
from main storage. When the initial data address in
the ccw is invalid, no data are transferred during the
operation, and the device is signaled to terminate the
operation in response to the first service request. On writing, devices such as magnetic tape units request
the first byte of data before any mechanical motion is
started and, if the initial data address is invalid, the
operation is terminated before the recording medium
has been advanced. However, since the operation has
been initiated, the device provides channel end, and
an interruption condition is generated. Whether a
block at the device is advanced when no data are
transferred depends on the type of device and is speci­ fied in the SRL publication for the device.
When command chaining takes place, the subchan­
nel appears in the working state from the time the first operation is initiated until the device signals the
channel-end condition of the last operation of the
chain. On the selector channel, the device executing
the operation stays connected to the channel and the
whole channel appears to be in the working state for
the duration of the execution of the chain of oper­
ations. On the multiplexor channel an operation in the
burst mode causes the channel to appear to be in the
working state only for the duration of the transfer of
the burst of data. If channel end and device end do
not occur concurrently, the device disconnects from
the channel after providing channel end, and the chan­
nel can in the meantime communicate with other de­
vices on the interface.
Any unusual conditions cause command chaining to
be suppressed and an interruption condition to be gen­
erated. The unusual conditions can be detected by
either the channel or the device, and the device can
provide the indications with channel end, control unit
end, or device end. When the channel is aware of the
unusual condition by the time the channel-end signal
for the operation is received, the chain is terminated
as if the operation during which the condition oc­
curred were the last operation of the chain. The de­
vice-end signal subsequently is processed as an inter­
ruption condition. When the device signals unit check
or unit exception with control unit end or device end,
the sub channel terminates the working state upon re-
Input/Output Operations 107
any interruption conditions while an operation is in
As soon as the selector channel has cleared the in­
terruption conditions associated with data transfer, it
starts scanning devices for attention, control-unit-end,
and device-end conditions and for the channel-end
condition associated with operations terminated by
HALT I/O. The highest priority is assigned to the I/O device that first identifies itself on the interface. On the multiplexor channel the priority among re­
quests for interruption is based only on the response
to scanning. The multiplexor channel continuously
scans its I/O devices. The highest priority is assigned
to the device that first responds with an interruption
condition or that requests service for data transfer and
contains the PCI condition in the subchannel. The PCI, as well as any other condition in the subchannel, can­
not cause an I/O interruption unless the device initiates
a reference to the subchannel.
Except for conditions associated with termination of
data transfer, the current assignment of priority for
interruption among devices on a channel may be can­
celed when START I/O or TEST I/O is issued to the chan­
nel. Whenever the assignment is canceled, the channel
resumes scanning for interruption conditions and re­
assigns the priority on completion of the activity as­
sociated with the I/O instruction.
The assignment of priority among requests for inter­
ruption from channels is based on the type of channel.
The priorities of selector channels are in the order of
their addresses, with channel 1 having the highest
priority. The interruption priority of the multiplexor
channel is not fixed and depends on the model and on
the current activity in the channel. Its priority may
be above, below, or between those of the selector
Interruption Action
An I/O interruption can occur only when the channel
accommodating the device is not masked and after the
execution of the current instruction in the CPU has
been terminated. If a channel has established the
priority among requests for interruption from devices
while it is masked, the interruption occurs immediate­
ly after the termination of the instruction removing
the mask and before the next instruction is executed.
This interruption is associated with the highest priority
condition on the channel. If more than one channel is
unmasked concurrently, the interruption occurs from
the channel having the highest priority among those
requesting interruption.
If the priority among interruption conditions has not
yet been established in the channel by the time the
mask is removed, the interruption does not necessarily 108 occur immediately after the termination of the instruc­
tion removing the mask. This delay can occur regard­
less of how long the interruption condition has existed
in the device or the subchannel.
The interruption causes the current program status
word (psw) to be stored as the old psw at location 56
and causes the csw associated with the interruption to
be stored at location 64. Subsequently, a new psw is
loaded from location 120, and processing resumes in
the state indicated by this psw. The I/O device causing
the interruption is identified by the channel address
in bit positions 21-23 and by the device address in bit
positions 24-31 of the old psw. The csw associated
with the interruption identifies the condition respon­
sible for the interruption and provides further details
about the progress of the operation and the status of
the device.
Programming Note
When a number of I/O devices on a shared control unit
are concurrently executing operations such as rewind­
ing tape or positioning a disk access mechanism, the
initial device-end signals generated on completion of
the operations are provided in the order of generation,
unless command chaining is specified for the operation
last initiated. In the latter case, the control unit pro­
vides the device-end signal for the last initiated op­
eration first, and the other signals are delayed until
the subchannel is freed. Whenever interruptions due
to the device-end signals are delayed either because
the channel is masked or the subchannel is busy, the
original order of the signals is destroyed. Channel Status Word
The channel status word (csw) provides to the pro­
gram the status of an I/O device or the conditions
under which an I/O operation has been terminated.
The csw is formed, or parts of it are replaced, in the
process of I/O interruptions and during execution of START I/O, TEST I/O, and HALT I/O. The csw is placed in
main storage at location 64 and is available to the pro­
gram at this location until the time the next I/O inter­
ruption occurs or until another I/O instruction causes
its content to be replaced, whichever occurs first.
When the csw is stored as a result of an I/O inter­
ruption, the I/O device is identified by the I/O address
in the old psw. The information placed in the csw by START I/O, TEST I/O, or HALT I/O pertains to the device
addressed by the instruction.
The csw has the following format: __ __________ C_om_m_a_n_d_A __ dd_r_es_s __ ---------.J 34 7 8 31
Status Count 4748 63
Previous Page Next Page