The key is effective only while the CPU is in the
stopped state. Storage-Select Switch The storage area to be addressed by the address
switches is selected by the storage-select switches.
The switch can select main storage, the general reg­
isters, the floating-point registers and, in some cases,
the instruction-address part of the psw.
When the general or floating-point registers are not
addressed directly but must be addressed by using
another address such as a local-store location, infor­
mation is included on the panel to enable an operator
to compute the required address.
The switch can be manipulated without disrupting CPU operations.
Address Switches
The address switches address a location in a storage
area and can be manipulated without disrupting CPU operation. The address switches, with the storage-se­
lect switch, permit access to any addressable location.
Correct address parity is generated.
Data Switches
The data switches specify the data to be stored in the
location specified by the storage-select switch and ad­
dress switches.
The number of data switches is sufficient to allow
storing of a full physical storage word. Correct data
parity is generated. Some models generate either cor­
rect or incorrect parity under switch control. Store Key
The store key is pressed to store information in the
location specified by the storage-select switch and ad­
dress switches.
The contents of the data switches are placed in the
main storage, general register, or floating-point .regis­
ter location specified. Storage protection is ignored.
When the location designated by the address switches
and storage-select switch is not available, data are not
stored.
The key is effective only while the CPU is in the
stopped state.
Display Key
The display key is pressed to display information in
the location specified by the storage-select switch and
address switches.
The data in the main storage, general register, or
floating-point register location, or in the instruction-
address part of the psw specified by the address
switches and the storage-select switch, are displayed.
When the designated location is not available, the dis­
played information is unpredictable. In some models,
the current instruction address is continuously dis­
played and hence is not explicitly selected.
The key is effective only while the CPU is in the
stopped state. Set IC Key
This key is pressed to enter an address into the in­
struction-address part of the current psw.
The key is effective only while the CPU is in the
stopped state.
The address in the address switches is entered in
bits 40-63 of the current psw. In some models the ad­
dress is obtained from the data switches. Address-Compare Switches
These rotary or key switches provide a means of stop­
ping the CPU on a successful address comparison.
When these switches are set to the stop position,
the address in the address switches is compared
against the value of the instruction address on all
models and against all addresses on some models. An
equal comparison causes the CPU to enter the stopped
state. Comparison includes only the part of the in­
struction address that addresses the physical word size
of storage.
Comparison of the entire halfword instruction ad­
dress is provided in some models, as is the ability to
compare data addresses.
The address-compare switches can be manipulated
without disrupting CPU operation other than by caus­
ing the address-comparison stop. When they are set
to any position but normal, the test light is on.
Programming Note
When an address not used in the program is selected
in the address switches, the CPU runs as if the address­
compare switches were set to normal, except for the
reduction in performance which may be caused by the
address comparison.
Alternate-Prefix Light
The alternate-prefix light is on when the prefix trigger
is in its alternate state. The light is part of the multi­
system feature.
Customer Engineering Section
This section of the system control panel contains con­
trols intended only for customer-engineering use. System Control Panel 121

Appenclix A. Instruction Use Examples The following examples illustrate the use of many System/360 instructions. Note that these examples
closely approximate machine language to best illus­
trate the operation of the system. For clarity, the
mnemonic for each operation code is used instead of
the actual machine code. In addition, whenever possi­
ble, the contents of registers, storage locations, and so
on, are given in decimal notation rather than the actual
binary formats. When binary formats are used, they
are segmented into bytes (eight bits) for ease of visual
comparison.
Included at the end of this Appendix are program­
ming examples that utilize the assembly language
symbols and formats'.
Load Complement The two's complement of general register 4 is to be
placed into general register 2.
Assume:
Condition code = 2; greater than zero
Reg 2 (before) 00000000 00000000 00000010 11010110 Reg 4 00000000 00000000 01001001 11010101 The instruction is: Op Code
LCR 2 4
Reg 2 (after) 1111111111111111 1011011000101011 Reg 2 contains the two's complement of Reg 4.
Condition code setting = 1; less than zero.
Load Multiple
General registers 5, 6, and 7 are to be loaded from
consecutive words starting at 3200. Assume:
Reg 5 (before)
Reg 6 (before)
Reg 7 (before)
Reg 12
Loc 3200-,3203 Loc 3204-3207 Loc 3208-3211 The instruction is: Op Code
LM
Reg 5 (after)
Reg 6 (after)
Reg 7 (after)
5
R.
7 Condition code: unchanged.
122
12 00 00 75 63 00 00 01 26 00 32 76 45 00 00 30 00 00 12 57 27 00 00 25 63
73 26 00 12
D2 200 00 12 57 27 00 00 25 63
73 26 00 12 Compare The contents of register 4 are to be algebraically com­
pared with the contents of register 2.
Assume:
Reg 2
Reg 4
The instruction is: Op Code
CR 4 2 00 00 03 92 00 00 03 47
Condition code = 1; first operand low.
Divide (Fixed Point)
The contents of the even/odd pair of general registers
6 and 7 are to be divided by the contents of general
register 4.
Assume:
Reg 6 (before) 00000000 00000000 00000000 00000000 ( 1st Word)
Reg 7 (before) 0000000000000000 0000100011011110 = +2270 (.2ndWord)
Reg 4 00000000 00000000 00000000 00110010 = + 50 The instruction is: Op Code
DR 6 4
Heg 6 (after) 000000000000000000000000 00010100 ( remainder) = +20 Heg 7 (after) 00000000 000000000000000000101101 (quotient) = +45
Condition code: unchanged.
The instruction divides the contents of registers 6
and 7 by the content of register 4. The quotient re­
places the content of register 7, and the remainder
replaces the content of register 6. Convert to Binary
The signed, packed decimal field at double-word loca­
tion 1000-1007 is to be converted into a binary integer
and placed in general register 7.
Assume:
Reg 5
Reg 6
Loe 1000-1007 Reg 7 (before) 00 00 00 50 00 00 09 00 00 00 00 00 00 25 59 4+
11111111 111000001111011110111111