NAME MNEMONIC TYPE EXCEPTIONS CODE NOTE Multiply
DecimalMP SS T P,A,S,D FC 5
Multiply
Halfword MH RXA,S 4C 2
Multiply (Long) N MDR RRFS,U,E 2C 3
Multiply (Long) N MD RXFA,S,U,E 6C 3,8
Multiply(Short) N MER RRF S,U,E 3C 3
Multiply(Short) N ME RXF A,S,U,E 7C 3,4 OR 0 RX C A,S 56 4 Set Storage Key SSK RRZ M, A,S 08 7 Shift Left
DoubleSLDA RS C S, IF 8F 1 Shift Left
Double
LogicalSLDL RS S 8D 1 Shift Right
DoubleSRDA RS C S 8E 1 Shift Right
Double
LogicalSRDL RS S 8C 1 Store ST RX P,A,S 50 4 Store IIalfword STH RX P,A,S 40 2 Store (Long) STD RXF P,A,S 60 3,8 Store Multiple STM RS P,A,S 90 4 Store (Short) STE RXF P,A,S 70 3,4
SubtractS RX C A,S, IF 5B 4
Subtract
HalfwordSH RX C A,S, IF 4B 2
Subtract
LogicalSL RX C A,S 5F 4
Subtract Norm-
alized (Long)NSDR RRF,C S,U,E,LS 2B 3
Subtract Norm-
alized (Long)NSD RXF,C A,S,U,E,LS 6B 3,8
Subtract Norm-
alized(Short) NSER RRF,C S,U,E,LS 3B 3
Subtract Norm-
alized(Short) NSE RXF,C A,S,U,E,LS 7B 3,4
SubtractUn- normalized
(Long)Subtract Un- SWR RRF,C S, E,LS 2F 3
normalized
(Long)SW RXF,C A,S, E,LS 6F 3,8
SubtractUn- normalized
(Short) SUR RRF,C S, E,LS 3F 3
SubtractUn- normalized
(Short) SU RXF,C A,S, E,LS 7F 3,4
The spccification interruption can occur in normal sequential
operation following branching,LOAD psw, intcrruption, or man-
ual operation (Note 1).
The spccification interruption can occur during an interruption
(Note 6).SPECIFICATION INTEnnUPTION NOTES 1 Even register spccification
2 Two-byte unit of information specification
3 Floating-point register specification
4 Four-bytc unit of information specification
5 Decimal multiplier or divisor size specification
6Zero protection key specification
7 Block address specification
8 Eight-byte unit of information specification
Data (D)
1. The sign or digit codes of operands in decimal
arithmetic, or editing operations, orCONVERT TO BINARY, are incorrect.
2. Fields in decimal arithmetic overlap incorrectly.
3. The decimal multiplicand has too many high
order significant digits.
The operation is terminated in all three cases.
The instruction-length code is 2 or 3.
NAMEMNEMONIC TYPE EXCEPTIONS CODE NOTE Add Decimal AP SST,C P,A, D, DF FA 1
Compare
DecimalCP SS T,C A, D F9 1
Convert to
BinaryCVB RX A,S,D IK 4F
Divide DecimalDP SS T P,A,S,D, DK FD 1
Edit EDSS T,C P,A, D DE
Edit and Mark EDMKSS T,C P,A, D DF
Multiply
DecimalMP SS T P,A,S,D FC 1,2
Subtract
DecimalSP SS T,C P,A, D, DF FB 1 Zero and Add ZAP SS T,C P,A, D, DF F8 1
All instructions listed may have incorrect codes.
DATAINTEHRUPTION NOTES 1 Overlapping fields 2 Multiplicand length
Fixed-Point Overflow (IF)
A high-order carry occurs or high-order significant bits
are lost in fixed-point addition, subtraction, shifting,
or sign-control operations.
The operation is completed by ignoring the infor
mation placed outside the register. The interruption
may be masked by psw bit 36.
The instruction-length code is 1 or 2.
NAMEMNEMONIC TYPE EXCEPTIONS CODE Add AR RR C IF 1A
Add A RX CA,S, IF 5A
Add Halfword AH RX CA,S, IF 4A
Load Complement LCR RR C IF 13
Load PositiveLPH RR C IF 10 Shift Left Double SLDA RS C S, IF 8F Shift Left Single SLA RS C IF 8B Subtract SR RR C IF IB Subtract S RX C A,S, IF 5B Subtract Halfword SH RX C A,S, IF 4B
Fixed-Point Divide(IK) 1. The quotient exceeds the register size in fixed
point division, including division by zero.
2. The result ofCONVERT TO BINARY exceeds 31 bits.
Division is suppressed. Conversion is completed by
ignoring the information placed outside the register.
The instruction -length code is 1 or 2.
NAMEMNEMONIC TYPE EXCEPTIONS CODE Convert to Binary CVB RX A,S,D, IK 4F
Divide DR RRS, IK ID Dividc D RX A,S, IK 5D
Appendix G 151
Decimal
Multiply
Halfword MH RX
Multiply (Long) N MDR RRF
Multiply (Long) N MD RXF
Multiply
Multiply
Double
Double
Logical
Double
Double
Logical
Subtract
Subtract
Halfword
Subtract
Logical
Subtract Norm-
alized (Long)
Subtract Norm-
alized (Long)
Subtract Norm-
alized
Subtract Norm-
alized
Subtract
(Long)
normalized
(Long)
Subtract
(
Subtract
(
The spccification interruption can occur in normal sequential
operation following branching,
ual operation (Note 1).
The spccification interruption can occur during an interruption
(Note 6).
2 Two-byte unit of information specification
3 Floating-point register specification
4 Four-bytc unit of information specification
5 Decimal multiplier or divisor size specification
6
7 Block address specification
8 Eight-byte unit of information specification
Data (D)
1. The sign or digit codes of operands in decimal
arithmetic, or editing operations, or
2. Fields in decimal arithmetic overlap incorrectly.
3. The decimal multiplicand has too many high
order significant digits.
The operation is terminated in all three cases.
The instruction-length code is 2 or 3.
NAME
Compare
Decimal
Convert to
Binary
Divide Decimal
Edit ED
Edit and Mark EDMK
Multiply
Decimal
Subtract
Decimal
All instructions listed may have incorrect codes.
DATA
Fixed-Point Overflow (IF)
A high-order carry occurs or high-order significant bits
are lost in fixed-point addition, subtraction, shifting,
or sign-control operations.
The operation is completed by ignoring the infor
mation placed outside the register. The interruption
may be masked by psw bit 36.
The instruction-length code is 1 or 2.
NAME
Add A RX C
Add Halfword AH RX C
Load Complement LCR RR C IF 13
Load Positive
Fixed-Point Divide
point division, including division by zero.
2. The result of
Division is suppressed. Conversion is completed by
ignoring the information placed outside the register.
The instruction -length code is 1 or 2.
NAME
Divide DR RR
Appendix G 151