Specification

Fixed-point overflow

Shift Right

78 1112 1516

The double-length integer part of the first 9perand is

shifted right the number of places specified by the

second operand address.

The

pair of registers and must contain an even register

address. A specification exception occurs when

odd.

The second operand address is not used to address

data; its low-order six bits indicate the number of bit

positions to be shifted. The remainder of the address

is ignored.

The sign of the first operand, which is leftmost in

the even register, remains unchanged. Bits equal to

the sign are supplied to the vacated high-order posi

tions of both registers. Low-order bits are shifted out

without inspection and are lost.

Resulting Condition Code:

o Result is zero

1 Result is less than zero

2 Result is greater than zero

3

Specification

Programming Note

A zero shift amount in the double-shift operations

provides a double-length sign and magnitude test.

fixed-Point Arithmetic Exceptions

Exceptional instructions, data, or results cause a pro

gram interruption. When a program interruption oc

curs, the current psw is stored as an old

new psw is obtained. The interruption code in the old

psw identifies the cause of the interruption. The

following exceptions cause a program interruption in

fixed-point arithmetic.

Protection: The storage key of a result location does

not match the protection key in the psw. The opera

tion is suppressed. Therefore, the condition code and

data in registers and storage remain unchanged. The

only exception is

the amount of data stored is unpredictable and should

not be used for further computation.

Addressing: An address designates a location out

side the available storage for a particular installation.

The operation is terminated. Therefore, the result data

are unpredictable and should not be used for further

computation.

used to address storage. Addresses used as a shift

amount are not tested. The address restrictions do not

apply to the components from which an address is

generated -thc content of the D2 field and the con

tents of the registers specified by X2 and

on a 64-bit boundary, a fuIlword operand is not located

on a 32-bit boundary, a halfword operand is not lo

cated on a 16-bit boundary, or an instruction specifies

an odd register address for a pair of general registers

containing a 64-bit operand. The operation is sup

pressed. Therefore, the condition code and data in reg

isters and storage remain unchanged.

Data: A sign or a digit code of the decimal operand

in

suppressed. Therefore, the condition code and data in

register and storage rcmain unchanged.

Fixed-Point

add, subtract, or shift operation overflows. The inter

ruption occurs only when the fixed-point overflow

mask bit is one. The operation is completed by placing

the truncated low-order result in the register and set

ting the condition code to 3. The overflow bits are lost.

In add-type operations the sign stored in the register

is the opposite of the sign of the sum or difference. In

shift operations the sign of the shifted number remains

unchanged. The state of the mask bit docs not affect

the result.

Fixed-Point Divide: The quotient of a division ex

ceeds the register size, including division by zero, or

the result in

sion is suppressed. Therefore, data in the registers

remain unchanged. The conversion is completed by re

cording the truncated low-order result in the register.