Program Interruptions:
Fixed-point overflow
Shift Right Double SRDA RS 8E
78 1112 1516 1920 31
The double-length integer part of the first 9perand is
shifted right the number of places specified by the
second operand address.
The RI field of the instruction specifies an even/odd
pair of registers and must contain an even register
address. A specification exception occurs when RI is
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
The sign of the first operand, which is leftmost in
the even register, remains unchanged. Bits equal to
the sign are supplied to the vacated high-order posi­
tions of both registers. Low-order bits are shifted out
without inspection and are lost.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Program Interruptions:
Programming Note
A zero shift amount in the double-shift operations
provides a double-length sign and magnitude test.
fixed-Point Arithmetic Exceptions
Exceptional instructions, data, or results cause a pro­
gram interruption. When a program interruption oc­
curs, the current psw is stored as an old PSW, and a
new psw is obtained. The interruption code in the old
psw identifies the cause of the interruption. The
following exceptions cause a program interruption in
fixed-point arithmetic.
Protection: The storage key of a result location does
not match the protection key in the psw. The opera­
tion is suppressed. Therefore, the condition code and
data in registers and storage remain unchanged. The
only exception is STORE MULTIPLE, which is terminated;
the amount of data stored is unpredictable and should
not be used for further computation.
Addressing: An address designates a location out­
side the available storage for a particular installation.
The operation is terminated. Therefore, the result data
are unpredictable and should not be used for further
computation. Operand addresses are tested only when
used to address storage. Addresses used as a shift
amount are not tested. The address restrictions do not
apply to the components from which an address is
generated -thc content of the D2 field and the con­
tents of the registers specified by X2 and B 2 Specification: A double-word operand is not located
on a 64-bit boundary, a fuIlword operand is not located
on a 32-bit boundary, a halfword operand is not lo­
cated on a 16-bit boundary, or an instruction specifies
an odd register address for a pair of general registers
containing a 64-bit operand. The operation is sup­
pressed. Therefore, the condition code and data in reg­
isters and storage remain unchanged.
Data: A sign or a digit code of the decimal operand
in CONVERT TO BINARY is incorrect. The operation is
suppressed. Therefore, the condition code and data in
register and storage rcmain unchanged.
Fixed-Point Overflow: The result of a sign-control,
add, subtract, or shift operation overflows. The inter­
ruption occurs only when the fixed-point overflow
mask bit is one. The operation is completed by placing
the truncated low-order result in the register and set­
ting the condition code to 3. The overflow bits are lost.
In add-type operations the sign stored in the register
is the opposite of the sign of the sum or difference. In
shift operations the sign of the shifted number remains
unchanged. The state of the mask bit docs not affect
the result.
Fixed-Point Divide: The quotient of a division ex­
ceeds the register size, including division by zero, or
the result in CONVERT TO BINARY exceeds 31 bits. Divi­
sion is suppressed. Therefore, data in the registers
remain unchanged. The conversion is completed by re­
cording the truncated low-order result in the register. Fixed-Point Arithmetic 33
Decimal Arithmetic
Decimal arithmetic operates on data in the packed
format. In this format, two decimal digits are placed
in one eight-bit byte. Since data are often communi­
cated to or from external devices in the zoned format
(which has one digit in an eight-bit byte), the neces­
sary format-conversion operations are also provided
in this instruction group.
Data are interpreted as integers, right-aligned in
their fields. They are kept in true notation with a sign
in the low-order eight-bit byte.
Processing takes place right to left between main­
storage locations. All decimal arithmetic instructions
use a two-address format. Each address specifics the
leftmost byte of an operand. Associated with this ad­
dress is a length field, indicating the number of addi­
tional bytes that the operand extends beyond the first
The decimal arithmetic instruction set provides for
adding, subtracting, comparing, multiplying, and di­
viding, as well as the format conversion of variable­
length operands. Most decimal instructions are part of
the decimal feature.
The condition code is set as a result of all add-type
and comparison operations.
Data Format
Decimal operands reside in main storage only. They
occupy Helds that may start at any byte address and
are composed of one to 16 eight-bit bytes.
Lengths of the two operands specified in an instruc­
tion need not be the same. If necessary they are con­
sidered to be extended with zeros to the left of the
high-order digits. Results never exceed the limits set
by address and length specification. Lost carries or
lost digits from arithmetic operations are signaled as
a decimal overflow exception. Operands arc either in
the packed or zoned format.
Packed Decimal Number I Digit I Digit I Digit Digit I Digit I Digit I Digit I Sign I In the packed format, two decimal digits normally are
placed adjacent in a byte, except for the rightmost
byte of the field. In the rightmost byte a sign is placed
to the right of decimal digit. Both digits and a sign
arc encoded and occupy four bits each. Zoned Decimal Number I Zone I Digit I Zone [-_- Digit I Zone I Digit I Sign In the zoned format the low-order four bits of a byte,
the numeric, are normally occupied by a decimal digit.
The four high-order bits of a byte are called the zone,
except for the rightmost byte of the field, where nor­
mally the sign occupies the zone position.
Arithmetic is performed with operands and results
in the packed format. In the zoned format, the digits
are represented as part of an alphameric character
set. A PACK instruction is provided to transform zoned
data into packed data, an an UNPACK instruction per­
forms the reverse transformation. Moreover, the edit­
ing instructions may be used to change data from
packed to zoned.
The fields specified in decimal arithmetic other than
in PACK, UNPACK, and MOVE WITH OFFSET either should
not overlap at all or should have coincident rightmost
bytes. In ZERO AND ADD, the destination field may also
overlap to the right of the source field. Because the
code configurations for digits and sign are verified
during arithmetic, improper overlapping fields are
recognized as data exceptions. In move-type oper­
ations, the operand digits and signs are not checked,
and the operand fields may overlap without any re­
The rules for overlapped fields are established for
the case where operands are fetched right to left from
storage, eight bits at a time, just before they are pro­
cessed. Similarly, the results are placed in storage,
eight bits at a time, as soon as they are generated.
Actual processing procedure may be considerably dif­
ferent because of the use of preferred storage for in­
termediate results. Nevertheless, the same rules are
Number Representation
Numbers are represented as right-aligned true integ­
ers with a plus or minus sign.
The digits 0-9 have the binary encoding 0000-1001. The codes 1010-1111 are invalid as digits. This set of
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