Store STE RX (Short Operands) I 70 R, I X
2 I B2 0 7 8 11 12 1516 1920 31 STD RX (Long Operands) I 60 R, I X
2 I B2 0 7 8 11 12 1516 1920 31
The first operand is stored at the second operand
In short-precision, the low-order half of the first op­
erand register is ignored. The first operand remains
Condition Code: The code remains unchanged. Program Interruptions: Operation (if floating-point feature is not in-
Protection Specification Floating-Point Arithmetic Exceptions
Exceptional instructions, data, or results cause a pro­
gram interruption. When the interruption occurs, the
current psw is stored as an old psw, and a new psw
is obtained. The interruption code in the old psw iden­
tifies the cause of the interruption. The following ex­
ceptions cause a program interruption in floating-point
Operation: The Floating-Point Feature is not in­
stalled, and an attempt is made to execute a floating­
point instruction. The instruction is suppressed. The
condition code and data in registers and storage re­
main unchanged. Protection: The storage key of a result location docs
not match the protection key in the psw. The opera­
tion is suppressed. Therefore, the condition code and
data in registers and storage remain unchanged.
Addressing: An address designates a location outside
the available storage for the installed system. The
operation is terminated. The result data and the con­
dition code, if affected, are unpredictable and should
not be used for further computation.
Specification: A short operand is not located on a
32-bit boundary or a long operand is not located on a
64-bit boundary; or, a floating-point register address
other than 0, 2, 4, or 6 is specified. The instruction is
suppressed. Therefore, the condition code and data
in registers and storage remain unchanged. The ad­
dress restrictions do not apply to the components from
which an address is generated -the content of the
D2 field and the contents of the registers specified by
X 2 and B 2 Exponent Overflow: The result exponent of an addi­
tion, subtraction, multiplication, or division overflows,
and the result fraction is not zero. The operation is
terminated; the result data are unpredictable and
should not be used for further computation. The con­
dition code is set to 3 for addition and subtraction and
remains unchanged for multiplication and division.
Exponent Underflow: The result of an addition, sub­
traction, multiplication, or division underflows, and the
result fraction is not zero. A program interruption oc­
curs if the exponent-underflow mask bit is one. The
operation is completed by replacing the result with
a true zero. The condition code is set to ° for addition
and subtraction and remains unchanged for multipli­
cation and division. The state of the mask hit does not
affect the result.
Significance: The result fraction of an addition or
subtraction is zero. A program interruption occurs if
the significance mask bit is one. The mask bit affects
also the result of the operation. When the significance
mask bit is a zero, the operation is completed by re­
placing the result with a true zero. When the signifi­
cance mask bit is one, the operation is completed
without further change to the characteristic of the
result. In either case, the condition code is set to 0. Floating-Point Divide: Division by a number with
zero fraction is attempted. The division is suppressed;
therefore, the condition code and data in registers and
storage remain unchanged.
Floating-Point Arithmetic 49
Logical Operations
A set of instructions is provided for the logical ma­ nipulation of data. Generally, the operands are treated
as eight-bit bytes. In a few cases the left or right four
bits of a byte are treated separately or operands are
shifted a bit at a time. The operands are either in
storage or in the general register. Some operands are
introduced from the instruction stream.
Processing of data in storage proceeds left to right
through fields which may start at any byte position. In
the general registers, the processing, as a rule, in­ volves the entire register contents.
Except: for the editing instructions, data are not
treated as numbers. Editing provides a transformation
from packed decimal digits to alphanumeric charac­ ters.
The set of logical operations includes moving, com­ paring, bit connecting, bit testing, translating, editing,
and shift operations. All logical operations other than
editing are part of the standard instruction set. Edit­ ing instructions are pali of the decimal feature.
The condition code is set as a result of all logical
comparing, connecting, testing, and editing operations.
Data Format
Data reside in general registers or in storage or are
introduced from the instruction stream. The data size
may be a single or double word, a single character, or
variable in length. When two operands participate
they have equal length, except in the editing instruc­ tions. Fixed-Lenuth Logical Information Logical Data
Data in general registers normally occupy all 32 bits.
Bits are treated uniformly, and no distinction is made
between sign and numeric bits. In a few operations,
only the low-order eight bits of a register participate,
leaving the remaining 24 bits unchanged. In some
shift operations, 64 bits of an even/odd pair of regis­ ters participate. 50 The LOAD ADDRESS introduces a 24-bit address into
a general register. The high-order eight bits of the
register are made zero.
In storage-to-register operations, the storage data
occupy either a word of 32 bits or a byte of eight bits.
The word must be located on word boundaries, that
is, its address must have the two low-order bits zero.
Variable-Length Logical Information
Character Character I Character
In storagc-to-storage operations, data have a variable
field-length format, starting at any byte address and
continuing for up to a total of 256 bytes. Processing
is left to right. Operations introducing data from the instruction
stream into storage, as immediate data, are restricted
to an eight-bit byte. Only one byte is introduced from
the instruction stream, and only one byte in storage
participates. Use of general register 1 is implied in TRANSLATE AND TEST and EDIT AND MARK. A 24-bit address may be
placed in this register during these operations. The TRANSLATE AND TEST also implies general register 2.
The low-order eight bits of register 2 may be replaced
by a function byte during a translate-and-test oper­ ation.
Editing requires a packed decimal field and gen­ erates zoned decimal digits. The digits, signs, and
zones are recognized and generated as for decimal
arithmetic. Otherwise, no internal data structure is re­ quired, and all bit configurations are considered valid.
The translating operations use a list of arbitrary
values. A list provides a relation between an argument
(the quantity used to reference the list) and the
function (the content of the location related to the
argument). The purpose of the translation may be to
convert data from one code to another code or to per­ form a control function.
A list is specified by an initial address -the address
designating the leftmost byte location of the list. The
byte from the operand to be translated is the argu­ ment. The actual address used to address the list is
obtained by adding the argument to the low-order po-
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