A set of operations is provided to switch the status of
theCPU, of storage, and of communication between
systems.
The over-allCPU status is determined by several
program-state alternatives, each of which can be
changed independently to its opposite and most of
which are indicated by a bit in the program status
word (psw). TheCPU status is further defined by the
instruction address, the condition code, the instruction
length code, the storage-protection key, and the inter
ruption code. These all occupy fields in the psw.
Storage is protected by storage keys, which are
matched with a protection key in the psw or in a chan
nel. The protcction status of storage may be changed
by introducing new storage keys, usingSET STORAGE KEY. The storage keys may be inspected by using IN SERT STORAGE KEY.
The system formed byCPU, storage, and I/O can
communicate with other systems by means of the sig
nals of the direct control feature and the multisystem
feature. The READ DIRECT makes signals available to
theCPU; WRITE DIRECT provides signals to other
systems.
All status-switching instructions, other than those of
the protection feature or direct control feature, are
provided in the standard instruction set.
Program States
The four types of program-state alternatives, which
determine the over-allCPU status, are named Problem/
Supervisor, Wait/Running, Masked/Interruptable, and
Stopped/Operating. These states differ in the way they
affect theCPU functions and in the way their status is
indicated and switched. Each state, except masked,
has one alternative.
All program states are independent of each other in
their function, indication, and status-switching. Status
switching does not affect the contents of the arith
metic registers or the execution ofI/O operations but
may affect the timer operation.Problem State
The choice between supervisor and problem state de
termines whether the full set of instructions is valid.
The names of these states reflect their normal use.
In the problem state allI/O, protection, and direct-
Status-Switch i ng
control instructions are invalid, as well asLOAD psw, SET SYSTEM MASK, and DIAGNOSE. These are called privi
leged instructions. A privileged instruction encount
ered in the problem state constitutes a privileged-op
eration exception and causes a program interruption.
In the supervisor state all instructions are valid.
When bit 15 of the psw is zero, theCPU is in the
supervisor state. When bit 15 is one, theCPU is in the
problem state. The supervisor state is not indicated on
the operator sections of the system control panel.
TheCPU is switched between problem and super
visor state by changing bit 15 of the psw. This bit can
be changed only by introducing a new psw. Thus
status-switching may be performed byLOAD psw, using
a new psw with the desired value for bit 15. SinceLOAD PSW is a privileged instruction, the CPU must be
in the supervisor state prior to the switch. A new psw
is also introduced when theCPU is interrupted. The SUPERVISOR CALL causes an interruption and thus may
change theCPU state. Similarly, initial program load
ing introduces a new psw and with it a newCPU state.
The new psw may introduce the problem or supervisor
state regardless of the preceding state. No explicit op
erator control is provided for changing the supervisor
state.
Timer updating is not affected by the choice be
tween supervisor and problem state.
Programming Note
To allow return from an interruption-handling routine
to a preceding program by aLOAD psw, the psw for
the interruption routine should specify the supervisor
state.
Wait State
In the wait state no instructions are processed, and
storage is not addressed repeatedly for this purpose,
whereas in the running state, instruction fetching and
execution proceed in the normal manner.
When bit 14 of thePSW, is one, the CPU is waiting.
When bit 14 is zero, theCPU is in the running state.
The wait state is indicated on the operator control
section of the system control panel by the wait light.
TheCPU is switched between wait and running state
by changing bit 14 of the psw. This bit can be changed
only by introducing an entire newPSW, as is the case
with the problem-state bit. Thus, switching from theStatus Switching 67
the
systems.
The over-all
program-state alternatives, each of which can be
changed independently to its opposite and most of
which are indicated by a bit in the program status
word (psw). The
instruction address, the condition code, the instruction
length code, the storage-protection key, and the inter
ruption code. These all occupy fields in the psw.
Storage is protected by storage keys, which are
matched with a protection key in the psw or in a chan
nel. The protcction status of storage may be changed
by introducing new storage keys, using
The system formed by
communicate with other systems by means of the sig
nals of the direct control feature and the multisystem
feature. The READ DIRECT makes signals available to
the
systems.
All status-switching instructions, other than those of
the protection feature or direct control feature, are
provided in the standard instruction set.
Program States
The four types of program-state alternatives, which
determine the over-all
Supervisor, Wait/Running, Masked/Interruptable, and
Stopped/Operating. These states differ in the way they
affect the
indicated and switched. Each state, except masked,
has one alternative.
All program states are independent of each other in
their function, indication, and status-switching. Status
switching does not affect the contents of the arith
metic registers or the execution of
may affect the timer operation.
The choice between supervisor and problem state de
termines whether the full set of instructions is valid.
The names of these states reflect their normal use.
In the problem state all
Status-Switch i ng
control instructions are invalid, as well as
leged instructions. A privileged instruction encount
ered in the problem state constitutes a privileged-op
eration exception and causes a program interruption.
In the supervisor state all instructions are valid.
When bit 15 of the psw is zero, the
supervisor state. When bit 15 is one, the
problem state. The supervisor state is not indicated on
the operator sections of the system control panel.
The
visor state by changing bit 15 of the psw. This bit can
be changed only by introducing a new psw. Thus
status-switching may be performed by
a new psw with the desired value for bit 15. Since
in the supervisor state prior to the switch. A new psw
is also introduced when the
change the
ing introduces a new psw and with it a new
The new psw may introduce the problem or supervisor
state regardless of the preceding state. No explicit op
erator control is provided for changing the supervisor
state.
Timer updating is not affected by the choice be
tween supervisor and problem state.
Programming Note
To allow return from an interruption-handling routine
to a preceding program by a
the interruption routine should specify the supervisor
state.
Wait State
In the wait state no instructions are processed, and
storage is not addressed repeatedly for this purpose,
whereas in the running state, instruction fetching and
execution proceed in the normal manner.
When bit 14 of the
When bit 14 is zero, the
The wait state is indicated on the operator control
section of the system control panel by the wait light.
The
by changing bit 14 of the psw. This bit can be changed
only by introducing an entire new
with the problem-state bit. Thus, switching from the