A set of operations is provided to switch the status of
the CPU, of storage, and of communication between
systems.
The over-all CPU status is determined by several
program-state alternatives, each of which can be
changed independently to its opposite and most of
which are indicated by a bit in the program status
word (psw). The CPU status is further defined by the
instruction address, the condition code, the instruction­
length code, the storage-protection key, and the inter­
ruption code. These all occupy fields in the psw.
Storage is protected by storage keys, which are
matched with a protection key in the psw or in a chan­
nel. The protcction status of storage may be changed
by introducing new storage keys, using SET STORAGE KEY. The storage keys may be inspected by using IN­ SERT STORAGE KEY.
The system formed by CPU, storage, and I/O can
communicate with other systems by means of the sig­
nals of the direct control feature and the multisystem
feature. The READ DIRECT makes signals available to
the CPU; WRITE DIRECT provides signals to other
systems.
All status-switching instructions, other than those of
the protection feature or direct control feature, are
provided in the standard instruction set.
Program States
The four types of program-state alternatives, which
determine the over-all CPU status, are named Problem/
Supervisor, Wait/Running, Masked/Interruptable, and
Stopped/Operating. These states differ in the way they
affect the CPU functions and in the way their status is
indicated and switched. Each state, except masked,
has one alternative.
All program states are independent of each other in
their function, indication, and status-switching. Status­
switching does not affect the contents of the arith­
metic registers or the execution of I/O operations but
may affect the timer operation. Problem State
The choice between supervisor and problem state de­
termines whether the full set of instructions is valid.
The names of these states reflect their normal use.
In the problem state all I/O, protection, and direct-
Status-Switch i ng
control instructions are invalid, as well as LOAD psw, SET SYSTEM MASK, and DIAGNOSE. These are called privi­
leged instructions. A privileged instruction encount­
ered in the problem state constitutes a privileged-op­
eration exception and causes a program interruption.
In the supervisor state all instructions are valid.
When bit 15 of the psw is zero, the CPU is in the
supervisor state. When bit 15 is one, the CPU is in the
problem state. The supervisor state is not indicated on
the operator sections of the system control panel.
The CPU is switched between problem and super­
visor state by changing bit 15 of the psw. This bit can
be changed only by introducing a new psw. Thus
status-switching may be performed by LOAD psw, using
a new psw with the desired value for bit 15. Since LOAD PSW is a privileged instruction, the CPU must be
in the supervisor state prior to the switch. A new psw
is also introduced when the CPU is interrupted. The SUPERVISOR CALL causes an interruption and thus may
change the CPU state. Similarly, initial program load­
ing introduces a new psw and with it a new CPU state.
The new psw may introduce the problem or supervisor
state regardless of the preceding state. No explicit op­
erator control is provided for changing the supervisor
state.
Timer updating is not affected by the choice be­
tween supervisor and problem state.
Programming Note
To allow return from an interruption-handling routine
to a preceding program by a LOAD psw, the psw for
the interruption routine should specify the supervisor
state.
Wait State
In the wait state no instructions are processed, and
storage is not addressed repeatedly for this purpose,
whereas in the running state, instruction fetching and
execution proceed in the normal manner.
When bit 14 of the PSW, is one, the CPU is waiting.
When bit 14 is zero, the CPU is in the running state.
The wait state is indicated on the operator control
section of the system control panel by the wait light.
The CPU is switched between wait and running state
by changing bit 14 of the psw. This bit can be changed
only by introducing an entire new PSW, as is the case
with the problem-state bit. Thus, switching from the Status Switching 67
running state may be achieved by the privileged in­
struction LOAD psw, by an interruption such as for SUPERVISOR CALL, or by initial program loading. Switch­
ing from the wait state may be achieved by an I/O or
external interruption or, again, by initial program
loading. The new psw may introduce the wait or run­
ning state regardless of the preceding state. No ex­
plicit operator control is provided for changing the
wait state.
Timer updating is not affected by the choice be­
tween running and wait state.
Programming Note
To leave the wait state without manual intervention,
the CPU should remain interruptable for some active I/O or external interruption source.
Masked States
The CPU may be masked or interruptable for all sys­
tems and machine-check interruptions and for some
program interruptions. When the CPU is interruptable
for a class of interruptions, these interruptions are
accepted. When the CPU is masked, the system inter­
ruptions remain pending, while the program and ma­
chine-check interruptions are ignored.
The system mask bits (psw bits 0-7), the program
mask bits (psw bits 36-39), and the machine-check
mask bit (psw bit 13) indicate as a group the masked
state of the CPU. When a mask bit is one, the CPU is
interruptible for the corresponding interruptions.
When the mask bit is zero, these interruptions are
masked off. The system mask bits indicate the masked
state of the CPU for the multiplexor channel, the six
selector channels, and the external signals. The pro­
gram mask bits indicate the masked state for four of
the 15 types of program exceptions. The machine­
check mask bit pertains to all machine checks. Pro­ gram interruptions not maskable, as well as the super­
visor-call interruption, are always taken. The masked
states are not indicated on the operator sections of the
system control panel.
"Most mask bits do not affect the execution of CPU operations. The only exception is the significance mask
bit, which determines the manner in which a Hoating­
point operation is completed when a significance ex­
ception occurs.
The interruptable state of the CPU is switched by
changing the mask bits in the psw. The program mask
may be changed separately by SET PROGRAM MASK, and
the system mask may be changed separately by the
privileged instruction SET SYSTEM MASK. The machine­
check mask bit can be changed only by introducing an
entire new PSW, as is the case with the problem-state
and wait-state bits. Thus, a change in the entire
68
masked status may be achieved by the privileged in­
struction LOAD psw, by an interruption such as for sup­ ERVISOR CALL, or by initial program loading. The new
psw may introduce a new masked state regardless of
the preceding state. No explicit operator control is
provided for changing the masked state.
Timer updating is not affected by the choice be­
tween masked or interruptable states.
Programming Note
To prevent an interruption-handling routine from be­ ing interrupted before necessary housekeeping steps
are performed, the new psw for that interruption
should mask the CPU for further interruptions of the
kind that caused the interruption.
Stopped State
When the CPU is in the stopped state, instructions and
interruptions are not executed. In the operating state,
the CPU executes instructions (if not waiting) and in­
telTui1tions (if not masked off).
The stopped state is indicated on the operator con­
trol section of the system control panel by the manual
light. The stopped state is not identified by a bit in
the psw.
A change in the stopped or operating state can be
effected only by manual intervention or by machine
malfunction. No instructions or interruptions can stop
or start the CPU. The CPU is commanded to stop when
the stop key on the operator intervention section of
the system control panel is pressed, when an address
comparison indicates equality, and when the rate
switch is set to INSTRUCTION STEP. In addition, the CPU is placed in the stopped state after power is turned on
or following a system reset, except during initial pro­
gram loading. The CPU is placed in the operating state
when the start key on the operator intervention panel
is pressed. The CPU is also placed in the operating
state when initial program loading is commenced.
The transition from operating to stopped state oc­
curs at the end of instruction execution and prior to
starting the next instruction execution. When the CPU is in the wait state, the transition takes place immedi­
ately. All interruptions pending and not masked off
are taken while the CPU is still in the operating state.
They cause an old psw to be stored and a new psw to
be fetched before entering the stopped state. Once the CPU is in the stopped state, interruptions are no longer
takcn but remain pending.
The timer is not updated in the stopped state.
Programming Notes
Except for timing considerations, execution of a pro­
gram is not affected by stopping the CPU.
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