base or index registers, from which the address is
generated. The use of the prefix applies both to ad­
dresses obtained from the program (CPU or I/O), and
to fixed addresses generated by the CPU for updating
or interruption purposes.
Both main prefix and alternate prefix occupy 12
bits. One or the other replaces the 12 high-order ad­
dress bits when these are found to be zero.
The choice of main or alternate prefix is determined
by the prefix trigger. This trigger is set during initial
program loading (IPL) and remains unchanged until
the next initial program loading occurs. Manual IPL sets the prefix trigger to the state of the prefix-select
switch on the operator. control section of the system
control panel. Electronic IPL sets the prefix trigger to
the state indicated by the signal line used. The state
of the prefix is indicated by the alternate-prefix light
on the operator intervention section of the system con­
trol panel.
The prefixes can be changed by hand within 5 min­
utes from one prewired encoding to another. The low­
order four bits of a prefix always have even parity,
and the total number of one-bits in a prefix cannot
exceed seven.
Malfunction Indication A machine check out-signal occurs whenever a ma­
chine check is recognized and the machine-check mask
bit is one. The signal has D.5-microsecond to l.O-micro­ second duration and is identical in electronic charac­
teristics to the signals on the signal-out lines of the
direct control feature.
The machine check out-signal is given during ma­
chine-check handling and has a high probability of
being issued in the presence of machine malfunction. System Initialization A main IPL in-line and an alternate IPL in-line respond
to O.5-microsecond to 1.0-microsecond pulses. Either
line, when pulsed, sets the prefix trigger to the state
indicated by its name and subsequently starts initial
program loading. Thus, these lines permit electronic
initiation of IPL. The definition of the signal to which these lines re­
spond is identical in electronic characteristic to the
definition for the signal-in lines of the external inter­
Instruction format
Status-switching instructions use the following two
RR Format I Op Code Rl R2 I 0 78 11 12 15
51 Format Op Code 12 Bl Dl
78 1516 1920 31
In the RR format, the Rl field specifies a general reg­
ister, except for SUPERVISOR CALL. The R2 field speci­
fies a general register in SET STORAGE KEY and INSERT STORAGE KEY. The Rl and R2 fields in SUPERVISOR CALL
contain an identification code. In SET PROGRAM MASK the R2 field is ignored.
In the SI format the eight-bit immediate field (12)
of the instruction contains an identification code. The h field is ignored in LOAD psw and SET SYSTEM MASK. The content of the general register specified by Bl is
added to the content of the Dl field to form an address
designating the location of an operand in storage. Only one operand location is required in status-switch­
ing operations.
A zero in the Bl field indicates the absence of the
corresponding address component.
The status-switching instructions and their mnemonics,
formats, and operation codes follow. The table also
indicates the feature to which an instruction belongs
and the exceptions that cause a program interruption.
NAME MNEMONIC TYPE EXCEPTIONS CODE Load PSW LPSW SI L M, A,S 82 Set Program Mask SPM RR L 04 Set System Mask SSM SI M, A 80 Supervisor Call SVC RR OA Set Storage Key SSK RR Z M, A,S 08 Insert Storage Key ISK RR Z M, A,S 09 Write Direct WRD SI Y M, A 84
Read Direct RDD SI Y M,P,A 85
Diagnose SI M, A,S 83 NOTES A Addressing exception
L New condition codc loaded
M Privileged-operation exception P Protection exception S Specification exception
Y Direct control feature Z Protection feature
Programming Note
The program status is also switched by interruptions,
initial program loading, and manual control. Status Switching 71
Load PSW LP5W 51
78 1516 1920 31
The double word at the location designated by the
operand address replaces the psw.
The operand address must have its three low-order
bits zero to designate a double word; otherwise, a
specification exception results in a program interrup­
The double word which is loaded becomes the psw
for the next sequence of instructions. Bits 40-63 of the
double word become the new instruction address. The
new instruction address is not checked for available
storage or for an even byte address during a load psw
operation. These checks occur as part of the execution
of the next instructions.
Bits 8-11 of the double word become the new pro­
tection key. The protection key must be zero when
the protection feature is not installed; otherwise, the
key is made zero, and a specification exception causes
a program interruption.
The interruption code in bit positions 16-31 of the
new psw is not retained as the psw is loaded. When
the psw is subsequently stored because of an interrup­
tion, these bit positions contain a new code. Similarly,
bits 32 and 33 of the psw are not retained upon load­ ing. They will contain the instruction-length code for
the last-interpreted instruction when the psw is stored
during a branch-and-link operation or during a pro­
gram or supervisor-call interruption.
Condition Code: The code is set according to bits
34 and 35 of the new psw loaded. Program Interruptions:
Privileged operation
Programming Note
The CPU enters the problem state when LOAD psw loads
a double word with a one in bit position 15 and sim­
ilarly enters the wait state if bit position 14 is one.
The LOAD psw is the only instruction available for
entering the problem state or the wait state.
72 Set Program Mask
5PM RR 04 78 11 12 15
Bits 2-7 of the general register specified by the Rl field replace the condition code and the program mask bits
of the current psw.
Bits 0, 1, and 8-31 of the register specified by the Rl field are ignored. The contents of the register specified
by the R 1 field remain unchanged.
The instruction permits setting of the condition code
and the mask bits in either the problem or supervisor
Condition Code: The code is set according to bits
2 and 3 of the register specified by R1. Program Interruptions: None.
Programming Note
Bits 2-7 of the general register may have been loaded
from the psw by BRANCH AND LINK. Set System Mask 5SM 51 80 78 1516 1920 31
The byte at the location designated by the operand
address replaces the system mask bits of the current
Condition Code: The code remains unchanged. Program Interruptions:
Privileged operation
Supervisor Call SVC RR I OA R] R2 I o 78 11 12 15
The instruction causes a supervisor-call interruption,
with the Rl and R2 field of the instruction providing
the intenuption code.
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