Control of Input/Output Devices
The CPU controls I/O operations by means of four I/O instructions: START I/O, TEST I/O, HALT I/O, and TEST CHANNEL.
The instruction TEST CHANNEL addresscs a channel;
it does not address an I/O device. The other three I/O instructions address a channel and a device on that
channel. Input/Output Device Addressing
An I/O device is designated by an I/O address. Each I/O address corresponds to a unique I/O device and is
specified by means of an II-bit binary number in the I/O instruction. The address identifies, for example, a
particular magnetic tape drive, disk access mcchanism,
or transmission line.
The I/O address consists of two parts: channel ad­
dress in the three high-order bit positions, and a device
address in the eight low-order bit positions. The chan­
nel address specifies the channel to which the instruc­
tion applies; the device address identifies the particular I/O device in that channel. Any number in the range 0-255 can be used as a device address, providing facili­
ties for addressing 256 devices per channel. The assign­
ment of I/O addresses is:
ADDRESS 000 xxxx xxxx 001 xxxx xxxx 010 xxx x xxxx 011. xxxx xxxx
1. 00 xxxx xxxx 101 xxx x xxxx
11 0 xxxx xxxx
111 xxxx xxxx
Devices on the multiplexor channel
Devices on selector channel 1
Devices on selector channel 2
Devices on selector channel 3
Devices on selector channel 4
Devices on selector channel 5
Devices on selector channel 6
Invalid On the multiplexor channel the device address
identifies the su bchannel as well as the I/O device. A
subchannel can be assigned a unique device address,
or it can be referred to by a group of addresses. When
more than one device address 'designates the same sub­
channel, the subchannel is called shared.
The following table lists the basic assignment of de­
vice addresses on the multiplexor channel. Addresses
with a zero in the high-order bit position pertain to
subchannels that are not shared. The seven low-order
bit positions of an address in this set identify one of
128 distinct subchannels. The presence of a one in the
high-order bit position of the address indicates that
the address refers to a shared sub channel. There are
eight such shared subchannels, each of which may be
shared by as many as 16 I/O devices. In addresses that
designate shared subchannels, the four low-order bit
positions identify the I/O device on the subchannel. ADDRESS 00000000 to 0111 1111 1000 xxxx 1001 xxxx 1.010 xxxx 1011 xxxx 1100 xxxx 1101. xxxx 1110 xxxx
1111 xxxx ASSIGNMENT Devices that do not share a subchannel
Devices on shared subchanncl 0 Devices on shared subchannel 1
Devices on shared subchanncl 2
Devices on shared subchannel 3
Devices on shared subchannel 4
Devices on shared subchannel 5
Devices on shared subchanncl 6
Devices on shared subchannel 7 Physically, the shared subchannels are the same as
the first eight non-shared subchannels. In particular,
the set of addresses 1000 xxxx refers to the same sub­
channel as the address 00000000, the set 1001 xxxx re­
fers to the same sub channel as the address 0000 0001, etc, while the set 1111 xxxx refers to the same subchan­
nel as the address 00000111. Thus, the installation of
all eight sets of devices on the shared subchannels re­
duces the maximum possible number of devices that
do not share a subchannel to 120. For devices sharing a control unit (for example,
magnetic tape units and the 2702 Transmission Con­ trol), the high-order bit positions of the device address
identify the control unit. The number of bit positions
in the common field depends upon the number of de­
vices installed but is designed to accommodate 16 or
the high-order bits of all addresses are common. Con­ trol units with more than 16 devices may be assigned
noncontiguous sets of 16 addresses. The low-order bit
positions of the address identify the device on the con­
trol unit.
When the control unit is designed to accommodate
fewer devices than can be addressed with the common
field, the control unit does not recognize the addresses
not assigned to it. For example, if a control unit is
designed to control devices having only bits 0000-1001 in the low-order positions, it does not recognize ad­
dresses containing 1010-1111 in these bit positions.
However, when a contra] unit has fewer than 16 de­
vices installed but is designed to accommodate 1 or
more, it may respond to all 16 addresses and may in­
dicate unit check for the invalid addresses.
Devices sharing both a control unit and a subchan­
nel ( magnetic tape units, disk access mechanism)
are always assigned as sets of 16 addresses, with four
high-order bits common. These addresses refer to the
same sub channel even if the control unit does not
recognize the whole set.
Input! output devices accessible through more than
one channel have a distinct address for each path of
communications. This address identifies the channel,
sub channel, and the control unit. For devices sharing
a control unit, the position of the address identifying
Input/Output Operations 87
the device on the control unit is fixed and does not de­
pend on the path of communications.
In models in which more than 128 sub channels are
available, the shared subchannels can optionally be re­
placed by sets of unshared subchannels. When the
option is implemented, the additional unshared sub­
channels are assigned sequential addresses starting at
Except for the rules described, the assignment of de­
vice addresses is arbitrary. The assignment is made at
the time of installation and normally is fixed.
Programmill1g Notes
Shared subchannels are used with devices, such as
magnetic tape units and disk access mechanisms, that
share a control unit. For such devices, the sharing of
the subchannel does not restrict the concurrency of I/O operations since the control unit permits only one de­
vice to be involved in a date transfer operation at a
The program can refer to a shared sub channel by
addresses 0-7 or by one of the addresses assigned to
the subchannel. No restrictions are imposed on the use
of a shared subchannel. If the subchannel is available,
the addressed device is selected, and the specified op­
eration is performed, regardless of the control unit to
which the device is attached. Instruction Exception Handling Before the channel is signaled to execute an I/O in­
struction, the instruction is tested for validity by the CPU. Exceptional conditions detected at this time cause
a program interruption. When the interruption occurs,
the current psw is stored as the old psw and is replaced
by a new psw. The interruption code in the old psw
identifies the cause of the interruption.
The following exception may cause a program inter­
ruption: Privileged Operation: An I/O instruction is encoun­
tered when the CPU is in the problem state. The in­
struction :is suppressed before the channel has been
signaled to execute it. The csw, the condition code in
the psw, and the state of the addressed sub channel
and I/O device remain unchanged. States of the Input/Output System The state of the I/O system identified by an I/O ad­
dress depends on the collective state of the channel,
sub channel, and I/O device. Each of these components
of the I/O system can have up to four states, as far as
the response to an I/O instruction is concerned. These
states are listed in the following table. The name of
the state is followed by its abbreviation and a brief
88 I/O DEVICE Available
Interruption pending
Not operational SUDCHANNEL Available
Interruption pending
Not operational CHANNEL Available
Interruption pending
A None of the following states
I Interruption condition pending in
W Device executing an operation
N Device not operational ADDREV DEFINITION
A None of the following states
I Information for CSW available in
W Subchannel executing an operation
N Subchannel not operational ADDREV DEFINITION
A None of the following states
I Interruption immediately available
from channel
W Channel operating in hurst mode
N Channel not operational
A channel, subchannel, or I/O device that is avail­
able, that contains a pending interruption condition, or
that is working, is said to be operational. The states of
containing an interruption condition, working, or be­
ing not operational are collectively referred to as "not available." In the case of the multiplexor channel, the channel
and subchannel are easily distinguishable and, if the
channel is operational, any combination of channel and
subchanncl states are possible. Since the selector chan­
nel can have only one subchannel, the channel and
subchannel are functionally coupled, and certain states
of the channel are related to those of the subchannel.
In particular, the working state can occur only concur­
rently in both the channel and subchannel and, when­
ever an interruption condition is pending in the sub­
channel, the channel also is in the same state. The
channel and sub channel, however, are not synony­
mous, and an interruption condition not associated
with data transfer, such as attention or device end,
does not affect the state of the subchannel. Thus, the
subchanne.1 may be available when the channel has
an interruption condition pending. Consistent dis­
tinction between the subchannel and channel permits
both types of channels to be covered uniformly by a
single description.
The device referred to in the preceding table in­
cludes both the device proper and its control unit. For
some types of devices, such as magnetic tape units, the
working and the interruption-pending states can be
caused by activity in the addressed device or control
unit. A shared control unit imposes its state on all de­
vices attached to the control unit. The states of the de­
vices are not related to those of the channel and sub­
When the response to an I/O instruction is deter­
mined on the basis of the states of the channel and
subchannel, the components further removed are not
interrogated. Thus, ten composite states are identified
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