The fixed-point instruction set performs binary arith­ metic on operands serving as addresses, index quanti­
ties, and counts, as well as fixed-point data. In general,
both operands are signed and 32 bits long. Negative
quantities are held in two's-complement form. One operand is always in one of the 16 general registers;
the other operand may be in main storage or in a
general register.
The instruction set provides for loading, adding,
subtracting, comparing, multiplying, dividing, and
storing, as well as for the sign control, radix conver­
sion, and shifting of fixed-point operands. The entire
instruction set is included in the standard instruction
set.
The condition code is set as a result of all sign­ control, add, subtract, compare, and shift operations.
Data Format
Fixed-point numbers occupy a fixed-length format
consisting of a one-bit sign followed by the integer
field. When held in one of the general registers, a
fixed-point quantity has a 31-bit integer field and oc­ cupies all 32 bits of the register. Some multiply, divide,
and shift operations use an operand consisting of 64
bits with a 63-bit integer field. These operands are
located in a pair of adjacent general registers and are
addressed by an even address referring to the left­ most register of the pair. The sign-bit position of the
rightmost register contains part of the integer. In reg­ ister-to-register operations the same register may be
specified for both operand locations.
Fullword Fixed-Point Number 151 Integer o 1 31
Halfword Fixed-Point Number I s\ Integer o 1 15
Fixed-point data in main storage occupy a 32-bit word
or a 16-bit halfword, with a binary integer field of 31
or 15 bits, respectively. The conversion instructions
Fixed-Point Arithmetic
use a 64-bit decimal field. These data must be located
on integral storage boundaries for these units of infor­ mation, that is, double-word, fullword, or halfword
operands must bc addressed with three, two, or one
low-ordcr address bit ( s) set to zero.
A halfword operand in main storage is extended to
a fullword as the operand is fetched from storage.
Subsequently, the operand participates as a full word
operand.
Number Representation
All fixed-point operands are treated as signed integers. Positive numbers are represented in true binary nota­ tion with the sign bit set to zero. Negative numbers
are represented in two's-complement notation with a
one in the sign bit. The two's complement of a num­ ber is obtained by inverting each bit of the number
and adding a one in the low-order bit position.
This type of number representation can be consider­
ed the low-order portion of an infinitely long represen­
tation of the number. When the number is positive, all
bits to the left of the most significant bit of the num­ ber, including the sign bit, are zeros. When the num­ ber is negative, all these bits, including the sIgn bit,
are ones. Therefore, when an operand must be ex­ tended with high-order bits, the expansion is achieved
by prefixing a field in which each bit is set equal to
the high-order bit of the operand.
Two's-complement notation does not include a nega­ tive zero. It has a number range in which the set of
negative numbers is one larger than the set of positive
numbers. The maximum positive number consists of
an all-one integer field with a sign bit of zero, whereas
the maximum negative number consists of an all-zero
integer field with a one-bit for sign.
The CPU cannot represent the complement of the
maximum negative number. When an operation, such
as a subtraction from zero, produces the complement
of the maximum negative number, the number remains
unchanged, and a fixed-pOint overflow exception is
recognized. An overflow does not result, however,
when the number is complemented and the final re­ suIt is within the representable range. An example of
this case is a subtraction from minus one. The product
of two maximum negative numbers is representable as
a double-length positive number.
Fixed-Point Arithmetic 23

The sign bit is leftmost in a number. An overHow
carries into the sign-bit position and changes the sign.
However, in algebraic shifting the sign bit does not
change even if significant high-order bits are shifted
out.
Programming Notes
Two's-complement notation is particularly suited to
address computation and multiple-precision arithmetic.
The two's-complement representation of a negative
number may be considered the sum of the integer
part of the field, taken as a positive number, and the
maximum negative number. Hence, in multiple-preci­
sion arithmetic the low-order fields should be treated
as positive numbers. Also, when negative numbers are
shifted to the right, the resulting rounding, if any, is
toward minus infinity and not toward zero.
Conditic)n Code
The results of fixed-point sign-control, add, subtract, compare" and shift operations are used to set the condi­
tion code in the program status word (psw). All other
fixed-point operations leave this code undisturbed.
The condition code can be used for decision-making
by subsequent branch-on-condition instructions.
The condition code can be set to reHect three types
of results for fixed-point arithmetic. For most opera­
tions, the states 0, 1, or 2 indicate a zero, less than
zero, or greater than zero content of the result reg­
ister' while the state 3 is used when the result over­
Hows.
For a comparison, the states 0, 1, or 2 indicate that
the first operand is equal, low, or high.
For ADD LOGICAL and SUBTRACT LOGICAL, the codes ° and 1 indicate a zero or nonzero result register con­
tent in the absence of a logical carry out of thc sign
position; the codes 2 and 3 indicate a zero or nonzero
result register content with a logical carry out of the
sign position. CONDITION CODE SETTINGS FOR FIXED-POINT ARITHMETIC 0 1 2 3
Add H/F zero < zero > zero overflow
Add Logical zero not zero zero, carry
carry Compare H/F equal low high
Load and Test zero < zero > zero
Load Complement zero < zero > zero overflow
Load Negative zero < zero
Load Positive zero > zero overflow
Shift Left Double zero < zero > zero overflow
Shift Left Single zero < zero > zero overflow
Shift Right Double zero < zero > zero
Shift Right Single zero < zero > zero
Subtract H/F zero < zero > zero overflow
Subtract Logical not zero zero, carry
carry
24
Instruction Format
Fixed-point instructions use the following three for­
mats:
RR Format
7 8 11 12 15
RX Format I Op Code Rl
X
2
B2 0 7 8 11 12 1516 1920 31
RS Format Op Code Rl R3 B2
7 8 11 12 1516 1920 31
In these formats, RJ specifies the address of the gen­
eral register containing the first operand. The second
operand location, if any, is defined differently for each
format.
In the HR format, the R2 field specifies the address of
the general register containing the second operand.
The same register may be specified for the first and
second operand.
In the RX format, the contents of the general reg­
isters specified by the X 2 and B2 fields are added to
the content of the D2 field to form an address designat­
ing the storage location of the second operand.
In the RS format, the content of the general register
specified by the B2 field is added to the content of the
D.) field to form an address. This address designates storage location of the second operand in LOAD MULTIPLE and STORE MULTIPLE. In the shift operations,
the address specifies the amount of shift. The field
specifics the address of a general register in LOAD MULTIPLE and STORE MULTIPLE and is ignored in the
shift operations.
A zero in an X 2 or B2 field indicates the absence of
the corresponding address component.
An instruction can specify the same general register
both for address modification and for operand loca­
tion. Address modification is always completed before
operation execution.
Results replace the first operand, except for STORE and CONVERT TO DECIMAL, where the result replaces
the second operand.
The contents of all general registers and storage
locations participating in the addressing or execution
part of an operation remain unchanged, except for the
storing of the final result.