operation code, but is stated explicitly, the informa
tion is said to have variable field length. Variable
length operands are variable in length by increments
of one byte.
Within any program format or any fixed-length op
erand format, the bits making up the format are con
secutively numbered from left to right starting with
the numberO. Byte Halfword 11 0 0 1 Jo 0 0 1 11 0 1 0 KO 0 1 01 15
Word11 0 0 011 0 0 111 0 0 0 BO 0 1 011 0 0 1'1> 1 0 011 1 1 0 1 11 16 24 31
Figure 2.Sample Information Formats
Addressing
Byte locations in storage are consecutively numbered
starting with0; each number is considered the ad
dress of the corresponding byte. A group of bytes in
storage is addressed by the leftmost byte of the group.
The addressing capability permits a maximum of
16,777,216 bytes, using a 24-bit binary address. This
set of main-storage addresses includes some locations
reserved for special purposes.
Storage addressing wraps around from the maximum
byte address, 16,777,215, to addressO. Variable-length
operands may be located partially in the last and par
tially in the first location of storage, and are processed
without any special indication.
When only a part of the maximum storage capacity
is available in a given installation, the available stor
age is normally contiguously addressable, starting at
addressO. An addressing exception is recognized
when any part of an operand is located beyond the
maximum available capacity of an installation.
In some models main storage may be shared by
more than oneCPU. In that case, the address of a byte
location is normally the same for eachCPU. Informatic)n Positioning Fixed-length fields, such as halfwords and double
words, must be located in main storage on an integral
boundary for that unit of information. A boundary is
called integral for a unit of information when its stor-
8
age address is a multiple of the length of the unit in
bytes. For example, words (four bytes) must be lo
cated in storage so that their address is a multiple of
the number 4. A halfword (two bytes) must have an
address that is a multiple of the number 2, and double
words (eight bytes) must have an address that is a
multiple of the number 8.
Storage addresses are expressed in binary form. In
binary, integral boundaries for halfwords, words, and
double words can be specified only by the binary ad
dresses in which one, two, or three of the low-order
bits, respectively, are zero. (Figure 3). For example,
the integral boundary for a word is a binary address
in which the two low-order positions are zero.
Varia ble fields are not limited to integral bounda
ries' but may start on any byte location.
Binary0000 0001 0010 0011 0100 01Ql 0110 0111 1000 1001 1010 Address
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte
Halfword Halfword Halfword Halfword Halfword, l Word Word Word -( Double-Word Double-Word
Figure 3. Integral Boundaries for Halfwords, Words, and
Doublewords
Central Processing Unit) l
The central processing unit (Figure 4) contains the
facilities for addressing main storage, for fetching or
storing information, for arithmetic and logical proc
essing of data, for sequencing instructions in the de
sired order, and for initiating the communication be
tween storage and external devices.
The system control section provides the normalCPU control that guides the CPU through the operation
necessary to execute the instructions. While the
physical make-up of the control section in the various
models of theSystems/360 may be different, the
logical function remains the same.
TheCPU provides 16 general registers for fixed-point
operands and four floating-point registers for floating
point operands. Implementation of these registers may
be in active elements, in a local storage unit, or in a
separate area of main storage. In each case, the ad
dress and functions of these registers are identical., l
tion is said to have variable field length. Variable
length operands are variable in length by increments
of one byte.
Within any program format or any fixed-length op
erand format, the bits making up the format are con
secutively numbered from left to right starting with
the number
Word
Figure 2.
Addressing
Byte locations in storage are consecutively numbered
starting with
dress of the corresponding byte. A group of bytes in
storage is addressed by the leftmost byte of the group.
The addressing capability permits a maximum of
16,777,216 bytes, using a 24-bit binary address. This
set of main-storage addresses includes some locations
reserved for special purposes.
Storage addressing wraps around from the maximum
byte address, 16,777,215, to address
operands may be located partially in the last and par
tially in the first location of storage, and are processed
without any special indication.
When only a part of the maximum storage capacity
is available in a given installation, the available stor
age is normally contiguously addressable, starting at
address
when any part of an operand is located beyond the
maximum available capacity of an installation.
In some models main storage may be shared by
more than one
location is normally the same for each
words, must be located in main storage on an integral
boundary for that unit of information. A boundary is
called integral for a unit of information when its stor-
8
age address is a multiple of the length of the unit in
bytes. For example, words (four bytes) must be lo
cated in storage so that their address is a multiple of
the number 4. A halfword (two bytes) must have an
address that is a multiple of the number 2, and double
words (eight bytes) must have an address that is a
multiple of the number 8.
Storage addresses are expressed in binary form. In
binary, integral boundaries for halfwords, words, and
double words can be specified only by the binary ad
dresses in which one, two, or three of the low-order
bits, respectively, are zero. (Figure 3). For example,
the integral boundary for a word is a binary address
in which the two low-order positions are zero.
Varia ble fields are not limited to integral bounda
ries' but may start on any byte location.
Binary
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte
Halfword Halfword Halfword Halfword Halfword
Figure 3. Integral Boundaries for Halfwords, Words, and
Doublewords
Central Processing Unit
The central processing unit (Figure 4) contains the
facilities for addressing main storage, for fetching or
storing information, for arithmetic and logical proc
essing of data, for sequencing instructions in the de
sired order, and for initiating the communication be
tween storage and external devices.
The system control section provides the normal
necessary to execute the instructions. While the
physical make-up of the control section in the various
models of the
logical function remains the same.
The
operands and four floating-point registers for floating
point operands. Implementation of these registers may
be in active elements, in a local storage unit, or in a
separate area of main storage. In each case, the ad
dress and functions of these registers are identical.