Input / Output Interruptions
Input/output interruptions provide a means for the CPU to change its state in response to conditions that
occur in I/O devices or channels. These conditions can
be caused by the program or by an external event at
the device.
Interruption Conditions
The conditions causing requests for I/O interruptions
to be initiated are called interruption conditions. An
interruption condition can be brought to the attention
of the program only once and is cleared when it causes
an interruption. Alternatively, an interruption con­
dition can be cleared by TEST I/O, and conditions gen­
erated by the I/O device following the termination of
the operation at the subchannel can be cleared by
START I/O. The latter include the attention, device-end,
and control-unit-end conditions, and the channel-end
condition when provided by a device on the selector
channel after termination of the operation by HALT I/O. The device initiates a request to the channel for an
interruption whenever it detects any of the following
conditions:
Channel end
Control unit end
Device end
Attention Unit check Unit exception
When command chaining is specified and is not sup­
pressed because of error conditions, channel end and
device end do not cause interruption conditions and
are not made available to the program. Unit-check and
unit-exception conditions cause interruption to be re­
quested only when the conditions are detected during
the initiation of a chained command. Once the com­
mand has been accepted by the device, unit check
and unit exception do not occur in the absence of
channel end, control unit end, or device end.
When the channel detects any of the following con­
ditions, it initiates a request for an I/O interruption
without having received the status byte from the de­
vice: PCI flag in a ccw.
Execution of HALT I/O on selector channel.
The interruption conditions from the channel can be
accompanied by other channel status indications, but
none of the device status bits is on when the channel
initiates the interruption.
A request for an I/O interruption due to a program­
check condition detected during command chaining
(such as invalid command code, count of zero, or two
sequential transfer-in-channel commands) may be ini­
tiated either by the I/O device or by the channel, de-
pending on the type of channel. To stack the inter­
ruption condition in the device, as occurs on the
multiplexor channel, the channel signals the device to
respond with a unit-status byte consisting of all zeros
on a subsequent scan for interruption conditions. The
error indication is preserved in the subchannel.
The method of processing a request for interruption
due to equipment malfunctioning, as indicated by the
presence of the channel-control-check and interface­
control-check conditions, depends on the model.
More than one interruption condition can be cleared
concurrently. As an example, when the PCI condition
exists in the subchannel at the termination of an oper­
ation, the PCI condition is indicated with channel end
and only one I/O interruption occurs, or only one TEST I/O is needed. Similarly, if the channel-end condition
is not cleared until device end is generated, both con­
ditions may be indicated in the csw and cleared at
the device concurrently.
However, at the time the channel assigns highest
priority for interruptions to a condition associated with
an operation at the subehannel, the channel accepts
the status from the device and clears the condition at
the device. The interruption condition is subsequently
preserved in the snbchannel. Any subsequent status
generated by the device is not included with the con­
dition at the suhchannel, even if the status is generated
before the CPU accepts the condition.
Priority of Interruptions
All requests for I/O interruption are asynchronous to
the activity in the CPU, and interruption conditions as­
sociated with more than one I/O device can exist at
the same time. The priority among requests is con­
trolled by two types of mechanisms -one establishes
the priority among interruption conditions associated
with devices attached to the same channel, and another
establishes priority among requests from different
channels. A channel requests an I/O interruption only
after it has established priority among requests from
its devices. The conditions responsible for the requests
are preserved in the dcvices or channels until accepted
by the CPU. Assignment of priority to requests for interruption
associated with devices on anyone channel is a func­
tion of the type of interruption condition and the po­
sition of the device on the I/O interface cable.
The selector channel assigns the highest priority to
conditions associated with the portion of the operation
in which the channel is involved. These conditions in­
clude channel end, program-controlled interruptions,
errors detected or command chaining, and execution
of HALT I/O in the channel. The channel cannot handle Input/Output Operations 105

ceipt of the signal from the device. The channel-end
indication in this case is not made available to the
program.
Termination by HALT I/O The instruction HALT r/ a causes the current operation
at the addressed channel or subchannel to be termi­
nated immediately. The method of termination differs
from that used upon exhaustion of count or upon de­
tection of programming errors to the extent that ter­
mination by HALT r/o is not contingent on the receipt
of a service request from the device.
When HALT r/o is issued to a channel operating in
the burst mode, the channel issues the haIt-r/o signal
to the device regardless of the current activity in the
channel and on the interface. If the channel is involved
in the data-transfer portion of an operation, data trans­
fer is immediately terminated, and the device is dis­
connected from the channel. If HALT I/O is addressed
to a selector channel executing a chain of operations
and the device has already provided channel end for
the current operation, the instruction causes the de­
vice to be disconnected and the chain-command Hag
to be removed.
When HALT I/O is issued to the multiplexor channel
and the channel is not operating in the burst mode,
the haIt-I/o signal is sent to the device whenever the
addressed subchannel is in the working state. The sub­
channel may be transferring data, or it may have al­
ready received channel end for the current operation
and may be waiting for device end to initiate a new
operation by command chaining. In either case, HALT
r/o causes the device to be selected, and the halt-I/o
signal is issued as the device responds. When com­
mand chaining is indicated in the subchannel, HALT I/O causes the chain-command Hag to be turned off.
Termination of an operation by HALT I/O on the se­
lector channel results in up to four distinct interrupt­
ion conditions. The first one is generated by the chan­
nel upon execution of the instruction and is not con­
tingent on the receipt of status from the device. The
command address and count in the associated csw
indicate how much data have been transferred, and
the channel-status bits reHect the unusual conditions
if any, detected during the operation. If HALT r/o issued before all data specified for the operation have
been transferred, incorrect length is indicated, subject
to the control of the SLI Hag in the current ccw. The
execution of HALT I/O itself is not reHected in csw
status, and all status bits in a csw due to this inter­
ruption condition can be zero. The channel is available
for the initiation of a new I/O operation as soon as the
interruption condition is cleared.
The second interruption condition on the selector
106
channel occurs when the control unit generates the
channel-end condition. The selector channel handles
this condition as any other interruption condition from
the device with the sub channel available and provides
zeros in the protection key, command address, count,
and channel status fields of the associated csw. The
channel-end condition is not made· available to the
program when HALT I/O is issued to a channel execu­
ting a chain of operations and the device has already
provided channel end for the current operation.
Finally, the third and fourth interruption conditions
occur when control unit end, if any, and device end
are generated. These conditions are handled as for any
other I/O operation.
Termination of an operation by HALT I/O on the
multiplexor channel causes the normal interruption
conditions to be generated. If the instruction is issued
when the subchannel is in the data-transfer portion of
an operation, the subchannel remains in the working
state until channel end is signaled by the device, at
which time the subchannel is placed in the interrupt­
ion-pending state. If HALT r/o is issued after the de­
vice has signaled channel end and the sub channel is
executing a chain of operations, the channel-end con­
dition is not made available to the program, and the sub channel remains in the working state until the next
status byte from the device is received. Receipt of a
status byte subsequently places the sub channel in the
interruption-pending state.
The csw associated with the interruption condition
in the sub channel contains the status bytes provided
by the device and the channel, and indicates at what
point data transfer was terminated. If HALT r/o is is­
sued before all data areas associated with the current
opcration have been exhausted or filled, incorrect
length is indicated, subject to the control of the SLI Hag in the current ccw. The interruption condition is
processed as for any other type of termination.
Termination Due to Equipment Malfunction
When channel equipment malfunctioning is detected
or invalid signals are received over the I/O interface,
the recovery procedure and the subsequent states of
the subchannels and devices on the channel depend
on the type of error and on the model. Normally, the
program is alerted of the termination by an I/O inter­
ruption, and the associated csw indicates the channel­
control-check or interface-control-check condition. In
channels sharing common equipment with the CPU, malfunctioning detected by the channel may be indi­
cated by a machine-check interruption, in which case
no csw is stored. Equipment malfunctioning may cause
the channel to perform the malfunction-reset function.