any interruption conditions while an operation is in
progress.
As soon as the selector channel has cleared the in­
terruption conditions associated with data transfer, it
starts scanning devices for attention, control-unit-end,
and device-end conditions and for the channel-end
condition associated with operations terminated by
HALT I/O. The highest priority is assigned to the I/O device that first identifies itself on the interface. On the multiplexor channel the priority among re­
quests for interruption is based only on the response
to scanning. The multiplexor channel continuously
scans its I/O devices. The highest priority is assigned
to the device that first responds with an interruption
condition or that requests service for data transfer and
contains the PCI condition in the subchannel. The PCI, as well as any other condition in the subchannel, can­
not cause an I/O interruption unless the device initiates
a reference to the subchannel.
Except for conditions associated with termination of
data transfer, the current assignment of priority for
interruption among devices on a channel may be can­
celed when START I/O or TEST I/O is issued to the chan­
nel. Whenever the assignment is canceled, the channel
resumes scanning for interruption conditions and re­
assigns the priority on completion of the activity as­
sociated with the I/O instruction.
The assignment of priority among requests for inter­
ruption from channels is based on the type of channel.
The priorities of selector channels are in the order of
their addresses, with channel 1 having the highest
priority. The interruption priority of the multiplexor
channel is not fixed and depends on the model and on
the current activity in the channel. Its priority may
be above, below, or between those of the selector
channels.
Interruption Action
An I/O interruption can occur only when the channel
accommodating the device is not masked and after the
execution of the current instruction in the CPU has
been terminated. If a channel has established the
priority among requests for interruption from devices
while it is masked, the interruption occurs immediate­
ly after the termination of the instruction removing
the mask and before the next instruction is executed.
This interruption is associated with the highest priority
condition on the channel. If more than one channel is
unmasked concurrently, the interruption occurs from
the channel having the highest priority among those
requesting interruption.
If the priority among interruption conditions has not
yet been established in the channel by the time the
mask is removed, the interruption does not necessarily 108 occur immediately after the termination of the instruc­
tion removing the mask. This delay can occur regard­
less of how long the interruption condition has existed
in the device or the subchannel.
The interruption causes the current program status
word (psw) to be stored as the old psw at location 56
and causes the csw associated with the interruption to
be stored at location 64. Subsequently, a new psw is
loaded from location 120, and processing resumes in
the state indicated by this psw. The I/O device causing
the interruption is identified by the channel address
in bit positions 21-23 and by the device address in bit
positions 24-31 of the old psw. The csw associated
with the interruption identifies the condition respon­
sible for the interruption and provides further details
about the progress of the operation and the status of
the device.
Programming Note
When a number of I/O devices on a shared control unit
are concurrently executing operations such as rewind­
ing tape or positioning a disk access mechanism, the
initial device-end signals generated on completion of
the operations are provided in the order of generation,
unless command chaining is specified for the operation
last initiated. In the latter case, the control unit pro­
vides the device-end signal for the last initiated op­
eration first, and the other signals are delayed until
the subchannel is freed. Whenever interruptions due
to the device-end signals are delayed either because
the channel is masked or the subchannel is busy, the
original order of the signals is destroyed. Channel Status Word
The channel status word (csw) provides to the pro­
gram the status of an I/O device or the conditions
under which an I/O operation has been terminated.
The csw is formed, or parts of it are replaced, in the
process of I/O interruptions and during execution of START I/O, TEST I/O, and HALT I/O. The csw is placed in
main storage at location 64 and is available to the pro­
gram at this location until the time the next I/O inter­
ruption occurs or until another I/O instruction causes
its content to be replaced, whichever occurs first.
When the csw is stored as a result of an I/O inter­
ruption, the I/O device is identified by the I/O address
in the old psw. The information placed in the csw by START I/O, TEST I/O, or HALT I/O pertains to the device
addressed by the instruction.
The csw has the following format: __ __________ C_om_m_a_n_d_A __ dd_r_es_s __ ---------.J 34 7 8 31
L
Status Count 4748 63

The fields in the csw are allocated for the following
purposes: Protection Key: Bits 0-3 form the storage protection
key used in the chain of operations initiated by the
last START I/O. Command Address: Bits 8-31 form an address that
is eight higher than the address of the last ccw used.
Status: Bits 32-47 identify the conditions in the de­
vice and the channel that caused the storing of the
csw. Bits 32-39 are obtained over the I/O interface and
indicate conditions detected by the device or the con­
trol unit. Bits 40-47 are provided by the channel and
indicate conditions associated with the subchannel.
Each of the 16 bits represents one type of condition,
as follows: nIT DESIGNATION BIT DESIGNATION
32 Attention 40 Pro gram -con trolled
interruption
33 Status modifier 41 Incorrcct length
34 Control unit end 42 Program check
35 Busy 43 Protection check
36 Channel end 44 Channel data check
37 Device end 45 Channel control check
38 Unit cheek 46 Interface control check
39 Unit exception 47 Chaining check
Count: Bits 48-63 form the residual count for the
last ccw used.
Unit Status Conditions The following conditions are detected by the I/O de­
vice or control unit and are indicated to the channel
over the I/O interface. The timing and causes of these
conditions for each type of device are specified in the SRL publication for the device.
When the I/O device is accessible from more than
one subchannel, status is signaled to the sub channel
that initiated the associated I/O operation. The han­
dling of conditions not associated with I/O operations
depends on the type of device and condition and is
specified in the SRL publication for the device.
The channel does not modify the status bits received
from the I/O device. These bits appear in the csw as
received over the interface.
Attention
Attention is caused upon the generation of the atten­
tion signal at the I/O device. The attention signal can
be generated at any time and is interpreted by the
program. Attention is not associated with the initiation,
execution, or termination of any I/O operation.
The attention condition cannot be indicated to the
program while an operation is in progress at the I/O device, control unit, or subchannel. Otherwise, the
handling and presentation of the condition to the chan­
nel depend on the type of device.
Status Modifier Status modifier is generated by the device when the
normal sequence of commands has to be modified or
when the control unit detects during the selection
sequence that it cannot execute the command or in­
struction as specified.
When the status-modifier condition is provided in
response to TEST I/O, presence of the bit indicates that
the device cannot execute the instruction and that no
bits pertaining to the current status of the device have
been provided. The status of the device and subchan­
nel is not changed, and the csw stored by TEST I/O contains zeros in the key, command address, channel
status, and count fields. The 2702 Transmission Con­ trol is an example of a type of device that cannot
execute TEST I/O. When the status-modifier bit appears in the csw to­
gether with the busy bit, it indicates that the busy
condition pertains to the control unit associated with
the addressed I/O device. The control unit appears
busy when it is executing a type of operation or is in
a state that precludes the acceptance of any command
or the instruction TEST I/O and HALT I/O. This occurs
for operations such as backspace tape file, in which
case the control unit remains busy after providing
channel end, and for operations terminated on the
selector channel by HALT I/O. The combination of
busy and status modifier can be provided in response
to any command as well as TEST I/O and HALT I/O. Presence of both busy and status modifier in response
to TEST I/O is handled the same way as when status
modifier alone is on. Once the execution of a command has been initi­
ated, the status-modifier indication can be provided
only together with device end. The handling of this
set of bits by the channel depends on the operation.
If command chaining is specified in the current ccw
and no unusual conditions have been detected, pres­
ence of the bit causes the channel to fetch and chain
to the ccw whose main-storage address is 16 higher
than that of the current ccw. If the I/O device signals
the status-modifier condition at a time when the chain­
command flag is off or when any unusual conditions
have been detected, no action is taken in the channel,
and the status-modifier bit is placed in the csw.
Programming Note
When the multiplexor channel detects a programming
error during command chaining, the interruption con­
dition is queued at the I/O device. On devices such as
the 2702 Transmission Control, queuing of the con­
dition may generate the status-modifier indication,
which subsequently appears in the csw associated
with the termination of the operation. Input/Output Operations 109