the condition responsible for the termination and may
or may not indicate incorrect length. When a data er­
ror has been detected before termination due to pro­
gram check, protection check, or chaining check, both
data check and the programming error are identified.
If the csw fetched on command chaining contains
the PCI flag but a programming error in the contents of
the csw or an unusual condition signaled by the de­
vice precludes the initiation of the operation, the PCI bit appears in the csw associated with the interruption
condition. Similarly, if device status or a programming
error in the contents of the ccw causes the command
to be rejected during execution of START I/O, the csw
stored by START I/O contains the PCI flag. The I/O flag,
however, is not included in the csw if a programming
error in the contents of the CAW prevents the oper­
ation from being initiated.
Conditions detected by the channel are not related
to those identified by the I/O device.
The following table summarizes the handling of
status bits. The table lists the states and activities that
can cause status indications to be created and the
methods by which these indications can be placed in
the csw.
TIME AND METHOD OF CREATING AND STORING STATUS INDICATIONS WHEN WHEN UPON TERMINATION OF OPERATION DURING BY BY BY BY I/O I/O IS SUB CHANNEL AT AT CONTROL AT COMMAND START TEST HALT INTER- STATUS IDLE WORKING SUBCIIANNEL UNIT DEVICE CHAINING I/O I/O I/O RUPTION ---------- Attention Co Status modifier
Control unit end
Busy
Channel end Co Device end Co Unit check C Unit exception C
Program-controlled interruption Co C
Incorrect length C C
Program check C C
Protection check C C
Channel data check Co C
Channel control check Co Co Co Interface control check Co Co Co Chaining check C C NOTES C-The channel or the device can create or present the status
condition at the indicated time. A CSW or its status portion is
not necessarily stored at this time.
Condition such as channel end and device end are created at
the indicated time. Other conditions may have been created
previously, but are made accessible to the program only at the
indicated time. Examples of such conditions are program check
and channel data check, which are detected while data are
transferred, but are made available to the program only with
channel end, unless the PCI flag or equipment malfunctioning
have caused an interruption condition to be generated earlier. S- The status indication is stored in the CSW at the indicated
time.
An S appearing alone indicates that the condition has been
created previously. The letter C appearing with the S indicates
that the status condition did not necessarily exist previously in
the form that causes the program to be alerted, and may have
116
C Co S S S C C CS CS CS S C1) CS CS CS S C CS CS CS S C1)H COt Ct S S S Co C l' C1' S s S C C Co CS CS CS C C Co CS S S C CS S S S S Co CS S S S S S S C1) Co Co CS CS CS CS C1) Co Co Cs CS Cs CS S S been created by the I/O instruction or I/O interruption. For
example, equipment malfunctioning may be detected during an I/O interruption, causing channel control check or interface
control check to be indicated; or a device such as the 2702 Transmission Control Unit may signal the control-un it-busy
condition in response to interrogation by an I/O instruction,
causing status modifier, busy, and control unit end to be indi­
cated in the CSW. 1) -The status condition generates or, in the case of channel
data check, may generate an interruption condition.
Channel end and device end do not result in interruption
conditions when command chaining is specified and no unusual
conditions have becn detected. 1'- This status indication can be created at the indicated time
only by an immediate operation.
II-When an operation on the selector channel has been termi­
natcd by HALT I/O, channel end indicates the termination of
thc datu-hundling portion of the operation at the control unit.

The system control panel contains the switches and
lights necessary to operate and control the system.
The system consists of the CPU, storage, channels, on­
line control units, and I/O devices. Off-line control
units and I/O devices, although part of the system
environment, are not considered part of the system
proper.
System controls are divided into three sections:
operator control, operator intervention, and customer
engineering control. Customer engineering controls
are also available on some storage, channel, and con­
trol-unit frames.
No provision is made for locking out any section of
the system control panel. The conditions under which
individual controls are active are described for each
case. System Control Functions
The system-reset function resets the CPU, the channels,
panel are the ability to reset the system; to store and
display information in storage, in registers and in the PSW; and to load initial program information.
System Reset
The system-reset function resets the CPU, the channels,
and on-line, nonshared control units and I/O devices.
The CPU is placed in the stopped state and all pend­
ing interruptions are eliminated. The parity of general
and floating-point registers, as well as the parity of the PSW, may be corrected. All error-status indicators are
reset to zero.
In general, the system is placed in such a state that
processing can be initiated without the occurrence of
machine checks, except those caused by subsequent
machine malfunction.
The reset state for a control unit or device is de­
scribed in the appropriate System Reference Library (SRL) publication. Off-line control units are not reset.
A system-reset signal from a CPU resets only the
functions in a shared control unit or device belonging
to that CPU. Any function pertaining to another CPU remains undisturbed.
The system-reset function is performed when the
system-reset key is pressed, when initial program
System Control Panel loading is initiated, or when a power-on sequence is
performed.
Programming Notes
Because the system reset may occur in the middle of
an operation, the contents of the psw and of result
registers or storage locations are unpredictable. If the CPU is in the wait state when the system reset is per­
formed, and I/O is not operating this uncertainty is
eliminated.
Following a system reset, incorrect parity may exist
in storage in all models and in the registers in some
models. Since a machine check occurs when informa­
tion with incorrect parity is used, the incorrect in­
formation should be replaced by loading new infor­
mation.
Store and Display The store-and-display function permits manual inter­
vention in the progress of a program. The store-and­
display function may be prOVided by a supervisor
program in conjunction with proper I/O equipment
and the interrupt key.
In the absence of an appropriate supervisor pro­
gram, the controls on the operator intervention panel
permit the CPU to be placed in the stopped state and
subsequently to store and display information in main
storage, in general and floating-point registers, and in
the instruction-address part of the psw. The stopped
state is achieved at the end of the current instruction
when the stop key is pressed, when single instruction
execution is specified, or when a preset address is
reached. Once the desired intervention is completed,
the CPU can be started again.
All basic store-and-display functions can be simu­
lated by a supervisor program. The stopping and start­
ing of the CPU in itself does not cause any alteration
in program execution other than the time element in­
volved (the transition from operating to stopped state
is described under "Stopped State" in "Status-Switch­ ing"). Interruption checks occurring during store-and-dis­
play functions do not interrupt or log immediately but
may, in some cases, create a pending interruption. This
interruption request can be removed by a system re­
set. Otherwise, the interruption, when not masked off,
is taken when the CPU is again in the operating state.
System Control Panel 117