Fixed Lengl'h Logical Information I Logical Data Variable-Length Logical Information I Character I Character 16 Character Figure 10. Fixed-Length and Variable-Length Logical
Information
31
( EBCDIC) (Figure 11) or the American Standard Code for Information Interchange (ASCII) extcnded to eight
bits (Figure 12).
The preferred codes do not have a graphic defined
for all 256 eight-bit codes. When it is desirable to rep­
resent all possible bit patterns, a hexadecimal repre­
sentation may be used instead of the preferred eight­
bit code. The hexadecimal representation uses one
graphic for a four-bit code, and therefore, two graph­
ics for an eight-bit byte. The graphics 0-9 are used
for codes 0000-1001; the graphics A-F are used for
codes 1010-1111. Bit Positions -,----. .. 01 L U:-
2
-3--
00
------, 4567 00 01 10 11 00 01 10 11 0000 NUL BLANK & - 0001 / 0010 0011 0100 PF RES BYP PN 0101 HT NL LF RS 0110 LC .BS EOB UC - 0111 DEL IDL PRE EOT 1000 -- 1001 , " 1010 ? ! : 1011 $ ,
# 1100 4--- * % @ 1101 ( ) ry-.. I 1110 + ;
-
=
1111 $ C7 +
j
-
Figure 11. Extended Binary-Coded-Decimal Interchange Code 12
Program Execution
The CPU program consists of instructions, index words,
and control words specifying the operations to be per­
formed. This information resides in main storage and
general registers, and may be operated upon as data. Instruction Format
The length of an instruction format can be one, two,
or three halfwords. It is related to the number of stor­
age addresses necessary for the operation. An instruc­
tion consisting of only one halfword causes no refer­
ence to main storage. A two-halfword instruction pro­
vides one storage-address specification; a three-half­
word instruction provides two storage-address specifi­
cations. All instructions must be located in storage on
integral boundaries for halfwords. Figure 13 shows
five basic instruction formats.
The five basic instruction formats are denoted by
the format codes RR, RX, RS, SI, and ss. The format
codes express, in general terms, the operation to be
performed. RR denotes a register-to-register operation;
RX, a register-to-indexed-storage operation; RS, a regis- 00 01 10 11 00 01 10 11 > < :j: 0 a
i
A J 1
b k s B K S 2
c I t C L T 3
d m u D
M U
4
e n v E N V 5
f 0 w F 0 W 6
9 P x G P X 7
h q y H
Q Y 8
i r z I R Z 9 1----- _._---

Bit Positions ---- •• 76
L I • X5 00------, 4321 00 01 10 11 01 00 01 10 11 00 01 10 ..----10-------.1 '--1 ----11-------. 11 00 01 10 11 0000 NULL DCa b a
blank (a) P 0001 50M DC
1 --- ,---- ----- - r----
A
- --- --- Q a q 0010 EOA DC
2 0011 EOM DC
3
2 41= 3
--
B R C 5
b r I---+----t-------f -------- C S -- 1------+----+ 0100 EOT DC4 5TOP $ 4 D T d t 0101 WRU ERR % 5 E U
e u --- ---- ----- 1---- -- -- - f-------f----J-----j 0110 RU 5YNC & 6 F V v 0111 BELL LEM -- ,------ ----"- ,
7 - f--- G W - --- - -- - ------- 9 W 1000 BK5P 50 1001 HT 51
8
9
H X --f-- - I Y f----- h x ---- 1----:- - - ---- I Y - I-- -- -----f-----, 1010 LF 52 J Z i z r------ ------+----__j --- 1011 VT 53 + K [ k 1100 FF 54 ---- L " r--·--r---+--1-- 1101 CR 55 M ::J m 1110 50 56 N
f r----- r- - -f- -- - ---
n E5C 1--- r- -- - - --1--- -I ---------- 1111 51 57 / ? 0 4-- o DEL
Figure 12. Eight-Bit Representation for American Standard Code for Information Interchange
for Use in Eight-Bit Environment
ter-to-storage operation; SI, a storage and immediate­
operand operation; and SS, a storage-to-storage oper­
ation.
For purposes of describing the execution of instruc­
tions, operands are designated as first and second op­ erands and, in the case of BRANCH ON INDEX, third op­
erands. These names refer to the manner in which the
operands participate. The operand to which a field in
an instruction format applies is generally denoted by
the number following the code name of the field, for
example, Rl, Bl, L 2 , D 2 • In each format, the first instruction halfword con­
sists of two parts. The first byte contains the oper­
ation code (op code). The length and format of an
instruction are specified by the first two bits of the
operation code.
INSTRUCTION LENGTH RECORDING
BIT POSITIONS INSTRUCTION INSTRUCTION <0-1) LENGTH FORMAT 00 One halfword RR 01 Two halfwords RX
10 Two halfwords RS or SI 11 Three halfwords SS The second byte is used either as two 4-bit fields
or as a single eight-bit field. This byte can contain the
following information:
Four-bit operand register specification Rb R 2 , or
R 3 )
Four-bit index register specification (X2)
Four-bit mask (M1)
Four-bit operand length specification (Ll or L2)
Eight-bit operand length specification (L)
Eight-bit byte of immediate data (12)
In some instructions a four-bit field or the whole sec­
ond byte of the first halfword is ignored.
The second and third halfwords always have the
same format:
Four-bit base register designator (Bl or B2), fol­ lowed by a 12-bit displacement (Dl or D2)'
Address Generation
For addressing purposes, operands can be grouped
in three classes: explicitly addressed operands in main
storage, immediate operands placed as part of the in- System Structure 13