Assume:
Reg 12
Reg 15
Loc2006-2010 (before)
Loc3007-3011 The instruction is: Op Code B, 00 00 20 00 00 00 30 00 Zl Z4 Z7 Z8 Z5
Y8 Y7 Y4 Y6 Y8
D,
6
Loc2006-2010 (after) Y1 Y4 Y7 Y8 Y5
Condition codc: unchanged.
AND (Register to Register)
When two operands are combined by an AND, they
are matched bit for bit. If corresponding bits are both
1, the result is 1. If either is0, the result is O. For
example, if the logical AND of register 5 and 6 is to
be taken,
Assume:Reg 6
Reg 5 (before)
The instruction is:Op Code RJ
NR 500000000000000000000000001011011 00000000000000000000000001110110 6 Reg 5 00000000 00000000 00000000 01010010 Condition code = 1; not all-zero result. OR When two operands are combined by an OR, they are
matched bit-for-bit. If either of the corresponding bits
is 1, the result is 1. If both are0, the result is O. For
example, if the logicalOR of register 5 and 6 is to be
taken,
Assume:
Reg 600000000 00000000 00000000 10110111 Reg 5 (before) 00000000 00000000 00000000 1110 11 0 1
The instruction is:Op Code OR 5 6
Heg 5 (after)00000000 00000000 00000000 11111111
Condition code = 1; not all-zero result.
ExclusiveOR When two operands are combined by an EXCLUSIVE OR, they are matched bit-for-bit. If the corresponding bits
match (both° or both 1), the result is O. If they differ,
the result is 1. For example, if theEXCLUSIVE OR of
register 5 and 6 is to be taken,
Assume:
Reg 600000000 00000000 00000000 10110111 Reg 5 (before) 00000000 00000000 00000000 111011 0 1
The instruction is:Op Code R, XR 5 6 Beg 5 (after) 00000000 00000000 00000000 01011010 Condition code = 1; not all-zero result.
TestUnder Mask
Test bit positions0, 2, 3, and 6 of a given byte in
storage to determine if all of these bit positions contain
ones. ATEST UNDER MASK with a mask of 10110010 ==
178
lO is used. The byte to be tested is stored at loca
tion1250 and contains 01101101. Assume: Beg 10 00 00 12 00 The instruction is: Op Code '" D, TM 178 10 50 t-.1ask from TM
Byte testcd
Selected result
Condition code
bits are 1.Insert Character 10110010 01101101 0- 10 -- 0- 1; some selected hits are 0, some selected
The character at location4200 is to be inserted into
the low-order eight bits of register 7.
Assume:
Reg 7 (before)
Heg4Reg 5
Loc4200 The instruction is: Op Code R, Ie 7 00000000 10110110 11000101 01101101 00 00 02 00 00 00 30 00 00001011 x, 4 5 1000 J
Reg 7 (after)00000000 101101101100010100001011 Condition code: unchanged.
Load Address
The effective address obtained by adding1000 to the
low-order 24 bits of general registers 3 and 2, is to be
placed in general register 4.
Assume:
Reg 4 (before)
Reg 3
Reg 2
The instruction is:Op Code LA 4 Reg 4 (after)
3
Condition code: unchanged.
73 1600 12 00 03 00 10 00 00 02 00 2 00 03 12 10 1000 Appendix A 125
Reg 12
Reg 15
Loc
Loc
Y8 Y7 Y4 Y6 Y8
D,
6
Loc
Condition codc: unchanged.
AND (Register to Register)
When two operands are combined by an AND, they
are matched bit for bit. If corresponding bits are both
1, the result is 1. If either is
example, if the logical AND of register 5 and 6 is to
be taken,
Assume:
Reg 5 (before)
The instruction is:
NR 5
matched bit-for-bit. If either of the corresponding bits
is 1, the result is 1. If both are
example, if the logical
taken,
Assume:
Reg 6
The instruction is:
Heg 5 (after)
Condition code = 1; not all-zero result.
Exclusive
match (both
the result is 1. For example, if the
register 5 and 6 is to be taken,
Assume:
Reg 6
The instruction is:
Test
Test bit positions
storage to determine if all of these bit positions contain
ones. A
178
lO is used. The byte to be tested is stored at loca
tion
Byte testcd
Selected result
Condition code
bits are 1.
The character at location
the low-order eight bits of register 7.
Assume:
Reg 7 (before)
Heg4
Loc
Reg 7 (after)
Load Address
The effective address obtained by adding
low-order 24 bits of general registers 3 and 2, is to be
placed in general register 4.
Assume:
Reg 4 (before)
Reg 3
Reg 2
The instruction is:
3
Condition code: unchanged.
73 16