Bit Positions ---- •• 76
LI • X5 00------, 4321 00 01 10 11 01 00 01 10 11 00 01 10 ..----10-------.1 '--1 ----11-------. 11 00 01 10 11 0000 NULL DCa b a
blank(a) P 0001 50M DC
1--- ,---- ----- - r----
A
- --- --- Q a q 0010 EOA DC
20011 EOM DC
3
241= 3
--
B RC 5
b rI---+----t-------f -------- C S -- 1------+----+ 0100 EOT DC4 5TOP $ 4 D T d t 0101 WRU ERR % 5 E U
e u--- ---- ----- 1---- -- -- - f-------f----J-----j 0110 RU 5YNC & 6 F V v 0111 BELL LEM -- ,------ ----"- ,
7- f--- G W - --- - -- - ------- 9 W 1000 BK5P 50 1001 HT 51
8
9
H X--f-- - I Y f----- h x ---- 1----:- - - ---- I Y - I-- -- -----f-----, 1010 LF 52 J Z i z r------ ------+----__j --- 1011 VT 53 + K [ k 1100 FF 54 ---- L " r--·--r---+--1-- 1101 CR 55 M ::J m 1110 50 56 N
fr----- r- - -f- -- - ---
n E5C1--- r- -- - - --1--- -I ---------- 1111 51 57 / ? 0 4-- o DEL
Figure 12. Eight-Bit Representation for American Standard Code for Information Interchange
forUse in Eight-Bit Environment
ter-to-storage operation; SI, a storage and immediate
operand operation; and SS, a storage-to-storage oper
ation.
For purposes of describing the execution of instruc
tions, operands are designated as first and secondop erands and, in the case of BRANCH ON INDEX, third op
erands. These names refer to the manner in which the
operands participate. The operand to which a field in
an instruction format applies is generally denoted by
the number following the code name of the field, for
example,Rl, Bl, L 2 , D 2 • In each format, the first instruction halfword con
sists of two parts. The first byte contains the oper
ation code (op code). The length and format of an
instruction are specified by the first two bits of the
operation code.
INSTRUCTION LENGTH RECORDING
BITPOSITIONS INSTRUCTION INSTRUCTION <0-1) LENGTH FORMAT 00 One halfword RR 01 Two halfwords RX
10 Two halfwordsRS or SI 11 Three halfwords SS The second byte is used either as two 4-bit fields
or as a single eight-bit field. This byte can contain the
following information:
Four-bit operand register specificationRb R 2 , or
R 3 )
Four-bit index register specification (X2)
Four-bit mask (M1)
Four-bit operand length specification (Ll or L2)
Eight-bit operand length specification (L)
Eight-bit byte of immediate data (12)
In some instructions a four-bit field or the whole sec
ond byte of the first halfword is ignored.
The second and third halfwords always have the
same format:
Four-bit base register designator (Bl or B2),fol lowed by a 12-bit displacement (Dl or D2)'
Address Generation
For addressing purposes, operands can be grouped
in three classes: explicitly addressed operands in main
storage, immediate operands placed as part of the in-System Structure 13
L
blank
1
A
-
2
3
2
--
B R
b r
e u
7
8
9
H X
f
n E5C
Figure 12. Eight-Bit Representation for American Standard Code for Information Interchange
for
ter-to-storage operation; SI, a storage and immediate
operand operation; and SS, a storage-to-storage oper
ation.
For purposes of describing the execution of instruc
tions, operands are designated as first and second
erands. These names refer to the manner in which the
operands participate. The operand to which a field in
an instruction format applies is generally denoted by
the number following the code name of the field, for
example,
sists of two parts. The first byte contains the oper
ation code (op code). The length and format of an
instruction are specified by the first two bits of the
operation code.
INSTRUCTION LENGTH RECORDING
BIT
10 Two halfwords
or as a single eight-bit field. This byte can contain the
following information:
Four-bit operand register specification
R 3 )
Four-bit index register specification (X2)
Four-bit mask (M1)
Four-bit operand length specification (Ll or L2)
Eight-bit operand length specification (L)
Eight-bit byte of immediate data (12)
In some instructions a four-bit field or the whole sec
ond byte of the first halfword is ignored.
The second and third halfwords always have the
same format:
Four-bit base register designator (Bl or B2),
Address Generation
For addressing purposes, operands can be grouped
in three classes: explicitly addressed operands in main
storage, immediate operands placed as part of the in-