Functions that May Differ Among Models Instruction Execution
In the editing operations, overlapping fields give un­
predictable results.
Equipment connected to the hold-in line of READ
DIRECT should be so constructed that the hold signal
will be removed when READ DIRECT is performed. Ex­
cessive duration of this instruction may result in in­
complete updating of the timer.
The purpose of the 12 field and the operand address
in the SI format of DIAGNOSE may be further defined
for a particular CPU and its appropriate diagnostic
procedures. Similarly the number of low-order address
bits that must be zero is further specified for a par­
ticular CPU. When the address does not have the re­
quired number of low-order zeros, a specification ex­
ception is recognized and causes a program interrup­
tion.
The diagnose operation is completed either by tak­
ing the next sequential instruction or by obtaining a
new psw from location 112. The diagnostic procedure
may affect the problem, supervisor, and interruptable
states of the CPU, and the contents of storage registers
and timer, as well as the progress of I/O operations. Instruction Termination Only one program interruption occurs for a given in­ struction. The old psw always identifies a valid cause.
This does not preclude simultaneous occurrence of
any other causes. Which of several causes is identified
may vary from one occasion to the next and from one
model to another.
When instruction execution is terminated by an in­
terruption, all, part, or none of the result may be
stored. The result data, therefore, are unpredictable.
The setting of the condition code, if called for, may
also be unpredictable. In general, the results of the
operation should not be used for further computation.
Cases of instruction termination for a program in­
terruption are:
Protection: The storage key of a result location does not match the protection key in the psw. The opera­
tion is terminated in the case of STORE MULTIPLE, READ
DIRECT, and variable-length operations. Protected stor­
age remains unchanged. The timing signals of READ
DIRECT may have been made available.
Addressing: An address specifies any part of data,
instruction, or control word outside the available stor­
age for the particular installation. The operation is
terminated. Data in storage remain unchanged, except
when designated by valid addresses.
156
Data: The sign or digit codes of operands in deci­
mal arithmetic, CONVERT TO BINARY, or editing opera­
tions are incorrect, or fields in decimal arithmetic over­
lap incorrectly, or the decimal multiplicand has too
many high-order significant digits. The operation is
terminated in all three cases. The condition code set­
ting, if called for, is unpredictable for protection, ad­
dressing, and data exceptions.
Exponent Overflow: The result exponent of an ADD, SUBTRACT, MULTIPLY, or DIVIDE overflows and the re­
sult fraction is not zero. The operation is terminated.
The condition code is set to 3 for ADD and SUBTRACT, and remains unchanged for MULTIPLY and DIVIDE. Machine-Check Interruption For a machine-check interruption, the old psw is
stored at location 48 with a zero interruption code.
The state of the CPU is scanned out into the storage
area starting with location 128 and extending through
as many words as are required by the given CPU. The
new psw is fetched from location 112. Proper execu­
tion of these steps depends Oil the nature of the ma­
chine check. A change in the machine-check mask bit
due to the loading of a new psw results in a change
in the treatment of machine checks. Depending upon
the nature of a machine check, the old treatment may
still be in force for several cycles. Machine checks that
occur in operations executed by I/O channels may
either cause a machine-check interruption or are re­
corded in the csw for that operation.
Instruction-Length Code The instruction-length code is predictable only for
program and supervisor-call interruptions. For I/O and
external interruptions, the interruption is not caused
by the last interpreted instruction, and the code is not
predictable for these classes of interruptions. For ma­
chine-check interruptions, the setting of the code is a
function of the malfunction and therefore unpredict­
able.
For the supervisor-call interruption the instruction­
length code is 1, indicating the halfword length of SUPERVISOR CALL; for the program interruptions, the
codes 1, 2, and 3 indicate the instruction length in
halfwords. The code 0 is reserved for program inter­
ruptions where the length of the instruction is not
available because of certain overlap conditions in in­
struction fetching. In those cases, the instruction ad­
dress in the old psw does not represent the next in­
struction address. The code 0 can
occur only for a program interruption caused by a
protected or unavailable data address.

Timer
Updating of the timer may be omitted when I/O data
transmission approaches the limit of storage capa­
bility.
System Control Panel The system-reset function may correct the parity of
general and floating-point registers, as well as the
parity of the psw.
The number of data switches is sufficient to allow
storing of a full physical storage word. Correct parity
generation is provided. In some models, either correct
or incorrect parity is generated under switch control.
The data in the storage, general register or floating­
point register location, or the instruction-address part
of the psw as specified by the address switches and
the storage-select switch can be displayed by the dis­
play key. When the location designated by the address
switches and storage-select switch is not available, the
displayed information is unpredictable. In some mod­
els, the instruction address is permanently displayed
and hence is not explicitly selected.
When the· address-comparison switches are set to
the stop position, the address in the address switches
is compared against the value of the instruction ad­
dress on some models, and against all addresses on
others. Comparison includes only that part of the in­
struction address corresponding to the physical word
size of storage.
Comparison of the entire halfword instruction ad­
dress is provided in some models, as is the ability to
compare data addresses.
The test light may be on when one or more diag­
nostic functions under control of DIAGNOSE are acti­
vated, or when certain abnormal circuit breaker or
thermal conditions occur. Normal Channel Operation
Channel capacity depends on the way I/O operations
are programmed and the activity in the rest of the
system. In view of this, an evaluation of the ability
of a specific I/O configuration to function concurrent­
ly must be based on the application. Two systems em­
ploying identical complements of I/O devices may be
able to execute certain programs in common, but it
is possible that other programs requiring, for example,
data chaining may not run on one of the systems.
The time when the interruption due to the PCI flag
occurs depends on the model and the current activity.
The channel may cause the interruption an unpredict­
able time after control of the operation is taken over
by the csw containing the PCI flag.
The content of the count field in a csw associated
with an interruption due to the PCI flag is unpredict­
able. The content of the count field depends upon the
model and its current activity.
When the channel has established which device on
the channel will cause the next I/O interruption, the
identity of the device is preserved in the channel. Ex­
cept for conditions associated with termination of an
operation at the subchannel, the current assignment
of priority for interruptions among devices mayor
may not be canceled when START r/o or TEST r/o is
issued to the channel, depending upon the model.
The assignment of priority among requests for in­
terruption from channels is based on the type of chan­
nel. The priorities of selector channels are in the order
of their addresses, with channel 1 having the highest
priority. The interruption priority of the multiplexor
channel is not fixed, and depends on the model and
the current activity in the channel. Channel Programming Errors
A data address referring to a location not provided in
the model normally causes program check when the
device offers a byte of data to be placed at the non­
existent location or requests a byte from that location.
Models in which the channel does not have the ca­
pacity to address 16,777,216 bytes of storage cause program check whenever the address is found to ex­
ceed the addressing capacity of the channel.
In the following cases, action depends on the ad­
dressing capacity of the model.
1. When the data address in the ccw deSignated
by the CAW exceeds the addressing capacity of the
model, the I/O operation is not initiated and the csw
is stored during the execution of START rio. Normally
an invalid data address does not preclude the initi­
ation of the operation.
2. When the data address in a ccw fetched during
command chaining exceeds the addressing capacity of
the model, the I/O operation is not initiated.
3. When a ccw fetched on data chaining contains
an address exceeding the addressing capacity of the
model and the device signals channel end immediate­
ly upon transferring the last byte designated by the
preceding ccw, program check is indicated to the pro­
gram. Normally, program check is not indicated un­
less the device attempts to transfer one more byte of
data.
4. Data addresses are not checked for validity dur­
ing skipping, except that the initial data address in
the ccw cannot exceed the addressing capacity of the
model.
When the channel detects program check or pro­
tection check, the content of the count field in the
associated csw is unpredictable.
Appendix G 157