Supervisor-Call Interruption
This interruption occurs as a result of execution of the
instruction SUPERVISOR CALL. Eight bits from the in­
struction format are placed in the interruption code
of the old psw, permitting a message to be associated
with the interruptions. A major use for the instruction SUPERVISOR CALL is to switch from the problem-state
to the supervisor state. This interruption may also be
used for other modes of status-switching.
External Interruption
The external interruption provides the means by
which the CPU responds to signals from the interrup­
tion key on the system control panel, the timer, and
the external signals of the direct control feature
(Figure 17). Interruption External
Code Bit I nterrupti on Cause Mask Bit
24 Timer
25 Interrupt key 7
26 External signal 6 7
27 External signal 5 7
28 External signal 4 7
29 External signal 3 7 30 External signal 2 7 3'1 External signal 1 7
Figure 17. Interruption Code for External Interruption
An external interruption can occur only when the
system mask bit 7 is one.
The source of the interruption is identified by the
interruption code in bits 24-31 of the psw. Bits 16-23
of the interruption code are made zero.
Machine-Check Interruption
The occurence of a machine check (if not masked
off) terminates the current instruction, initiates a diag­
nostic procedure, and subsequently causes the ma­
chine-check interruption. A machine check cannot be
caused by invalid data or instructions. The diagnostic
scan is performed into the scan area starting at lo­
cation 128. Proper execution of these steps depends
on the nature of the machine check.
Priority of Interruptions
During execution of an instruction, several interrup­
tion requests may occur simultaneously. Simultaneous
interruption requests are honored in the following pre­
determined order:
Machine Check Program or Supervisor Call
External Input/Output The program and supervisor-call interruptions are
mutually exclusive and cannot occur at the same time.
When more than one interruption cause requests
service, the action consists of storing the old psw and
fetching the new psw belonging to the interruption
which is taken first. This new psw subsequently is
stored without any instruction execution and the next
interruption psw is fetched. This process continues
until no more interruptions are to be serviced. When
the last interruption request has been serviced, in­
struction execution is resumed using the psw last
fetched. The order of execution of the interruption
subroutines is, therefore, the reverse of the order in
which the psw's are fetched.
Thus, the most important interruptions - I/O, ex­
ternal, program or supervisor call -are actually serv­
iced first. Machine check, when it occurs, does not al­
low any other interruptions to be taken.
Program States Over-all CPU status is determined by four types of pro­
gram-state alternatives, each of which can be changed
independently to its opposite and most of which are
indicated by a bit or bits in the psw. The program­
state alternatives are named stopped or operating,
running or waiting, masked or interruptable, and sup­
ervisor or problem state. These states differ in the way
they affect the CPU functions and the manner in which
their status is indicated and switched. All program
states are independent of each other in their functions,
indication, and status-switching. Stopped or Operating States: The stopped state is
entered and left by manual procedure. Instructions are
not executed, interruptions are not accepted, and the
timer is not updated. In the operating state, the CPU is capable of executing instructions and being inter­
rupted.
Running or Waiting State: In the running state, in­
struction fetching execution proceeds in the normal
manner. The wait state is normally entered by the
program to await an interruption, for example, an I/O interruption or operator intervention from the console.
In the wait state, no instructions are processed, the
timer is updated, and 110 and external interruptions
are accepted, unless masked. Running or waiting state
is determined by the setting of bit 14 in the psw. Masked or Interruptable State: The CPU may be in­
terruptable or masked for the system, program, and
machine interruptions. \Vhen the CPU is interruptable
for a class of interruptions, these interruptions are ac­
cepted. When the CPU is masked, the system inter­
ruptions remain pending, while the program and ma­
chine-check interruptions are ignored. The interrupt­
able states of the CPU are changed by changing the
mask bits of the psw.
System Structure 17

Supervisor or Problem State: In the problem state,
all 110 instructions and a group of control instructions
are invalid. In the supervisor state, all instructions
are valid. The choice of problem or supervisor state is
determined by bit 15 of the psw.
Protection feature
The Protection Feature protects the contents of cer­
tain areas of storage from destruction due to errone­
ous storing of information during the execution of a
program. This protection is achieved by identifying
blocks of storage with a storage key and comparing
this key with a protection key supplied with the data
to be stored. The detection of a mismatch results in
a protection interruption.
For protection purposes, main storage is divided in­
to blocks of 2,048 bytes. A four-bit storage key is as­
sociated with each block. When data are stored in a
storage block, the storage key is compared with the
protection key. When storing is specified by an in­
struction, the protection key of the current psw is
used as the comparand. When storing is specified by
a channel operation, a protection key supplied by the
channel iis used as the comparand. The keys are said
to match when they are equal or when either one is
zero.
The storage key is not part of addressable storage.
The key is changed by SET STORAGE KEY and is in­
spected by INSERT STORAGE KEY. The protection key in
the psw occupies bits 8-11 of that control word. The
protection key of a channel is recorded in bits 0-3 of
the csw, which is stored as a result of the channel
operation. When a protection mismatch due to an in­
struction is detected, the execution of this instruction
is suppressed or terminated, and the program execu­
tion is altered by an interruption. The protected stor­
age location always remains unchanged. Protection mismatch due to an 110 operation causes the data
transmission to be terminated in such a way that the
protected storage location remains unchanged. The
mismatch is indicated in the csw stored as a result of
the operation.
Timer f'eature
The timer is provided as an interval timer and may
be programmed to maintain the time of day. The
timer consists of a full word in main storage location 80. The timer word is counted down at a rate of 50 or 60 cycles per second, depending on line frequency.
The timer word is treated as a signed integer follow­
ing the rules of fixed-point arithmetic. An external in­
terruption condition is signaled when the value of the
18
timer word goes from positive to negative. The full
cycle time of the timer is 15.5 hours.
An updated timer value is available at the end of
each instruction execution but is not updated in the
stopped state. The timer is changed by addressing
storage location 80. As an interval timer, the timer is
used to measure elapsed time over relatively short in­
tervals. It can be set to any value at any time.
Direct Control feature
The direct control feature provides two instructions,
READ DIRECT and WRITE DIRECT, and six external inter­
ruption lines. The read and write instructions provide
for the transfer of a single byte of information be­
tween an external device and the main storage of the
system. It is usually most desirable to use the data
channels of the system to handle the transfer of any
volume of information and u.se the direct data control
feature to pass controlling and synchronizing informa­
tion between the CPU and special external devices.
Each of the six external signal lines, when pulsed,
sets up the conditions for an external interruption.
Multisystem feature
The design of System/360 permits communication be­
tween individual cpu's at several transmission rates.
The communication is possible through shared con­
trol units, through a channel connector and through
shared storage. These features are further augmented
by the direct control feature and the multisystem
feature. The direct control feature, described in
the previous section, can be used to signal from one CPU to another. The multisystem feature provides di­
rect address relocation, malfunction indications, and
electronic CPU initialization.
The relocation procedure applies to the first 4,096 bytes of storage. This area contains all permanent
storage assignments and, generally, has special signifi­
cance to supervisory programs. The relocation is ac­
complishcd by inserting a 12-bit prefix in each address
which has the high-order 12 bits set to zero and hence,
pertains to location 0-4095. Two manually set prefixes
are available to permit the use of an alternative area
when storage malfunction occurs. The choice between
the prefixes is determined by a prefix trigger set dur­
ing initial program loading.
To alert one CPU to the possible malfunction of an­
other CPU, a machine check-out signal is provided,
which can serve as an external interruption to another cpu. Finally, the feature includes provision for initial
program loading initiated by a signal from another CPU.