Instructions
The fixed-point arithmetic instructions and their mne-
monics, formats, and operation codes are listed in the
following table. The table also indicates which instruc-
tions are not included in the small binary instruction
set, when the condition code is set, and the exceptional
conditions that cause a program interruption.
NAME MNEMONIC Load LR
Load L
Load Halfword LH
Load and Test LTR
Load Complement LCR Load Positive LPR Load Negative LNR
Load Multiple LM
Add AR
Add A
Add Halfword All
Add Logical ALR
Add Logical AL Subtract SR Subtract S Subtract Halfword SH Subtract Logical SLR Subtract Logical SL Compare CR Compare C Compare Halfword CH Multiply MR
Multiply M
Multiply Halfword MH
Divide DR
Divide D Convert to Binary CVB Convert to Decimal CVD Store ST Store Halfword STH Store Multiple STM Shift Left Single SLA Shift Right Single SRA Shilt Left Double SLDA Shift Right Double SRDA Addressing exception
Condition code is set
Data exception
TYPE
RR
RX
RX
RR
RR
RR
RR RS RR
RX
RX
RR
RX
RR
RX
RX
RR
RX
RR
RX
RX
RR
RX
RX
RR
RX
RX
RX
RX
RX RS RS RS RS RS NOTES A C D
IF
IK P S Fixed-Point overflow exception
Fixed-point divide exception Protection exception
Specification exception
Programming Note EXCEPTIONS A,S A,S C C IF C IF C A,S C IF C A,S, IF C A,S, IF C C A,S C IF C A,S, IF C A,S, IF C C A,S C C A,S C A,S S A,S A,S S, IK A,S, IK A,S,D,IK P,A,S P,A,S P,A,S P,A,S C IF C C S, IF C S CODE 18
58
48
12
13 10 11
98
lA
5A
4A
IE
5E
IB
5B
4B
IF
5F
19
59
49
Ie 5C 4C ID
5D
4F
4E 50 40 90 8B
8A
8F
8E
The logical comparisons, shifts, and connectives, as
well as LOAD ADDRESS, BRANCH ON COUNT, BRANCH ON INDEX HIGH, and BRANCH ON INDEX LOW OR EQUAL, also
may be used in fixed-point calculations.
Load
LR RR I 18 R1 R2 0 7 8 11 12 15
L RX I 58 R1
X
2
B2 D2 0 7 8 11 12 1516 1920 31
The second operand is placed in the first operand loca­
tion. The second operand is not changed.
Condition Code: The code remains unchanged.
Program Interruptions:
Addressing (L only)
Specification (L only)
Load Halfword
LH RX
48
7 8 11 12 15 16 1 9 20 31
The halfword second operand is placed in the first
operand location.
The halfword second operand is expanded to a full­
word by propagating the sign-bit value through the
16 high-order bit positions. Expansion occurs after the
operand is obtained from storage and before insertion
in the register.
Program Interruptions:
Addressing
Specification
Load and Test
LTR RR
12
7 8 11 12 15
The second operand is placed in the first operand loca­
tion, and the sign and magnitude of the second op­
erand determine the condition code. The second op­
erand is not changed. Fixed-Point Arithmetic 25

Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3
Program Interruptions: None.
Programming Note
When the same register is specified as first and second
operand location, the operation is equivalent to a test
without data movement.
Load Complement LCR RR. 13
78 1112 15
The two's complement of the second operand is placed
in the first operand location.
An overflow condition occurs when the maximum
negative number is complemented; the number re­
mains unchanged. The overflow causes a program in­
terruption when the fixed-point overflow mask bit is
one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow Program Interruptions:
Fixed-point overflow Programming Note Zero rema.ins invariant under complementation.
Load Posit'ive LPR RR 10 78 1112 15
The absolute value of the second operand is placed in
the first operand location.
The operation includes complementation of nega­
tive numbers; positive numbers remain unchanged.
An overflow condition occurs when the maximum
negative number is complemented; the number re­
mains unchanged. The overflow causes a program in­
terruption when the fixed-point overflow mask bit is
one.
26
Resulting Condition Code:
o Result is zero
1
2 Result is greater than zero
3 Overflow Program Interruptions:
Fixed-point overflow Load Negative
LNR RR
11
78 1112 15
The two's complement of the absolute value of the
second operand is placed in the first operand location.
The operation complements positive numbers; nega­
tive numbers remain unchanged. The number zero
remains unchanged with positive sign.
Resulting Condition Code:
o Result is zero
1 Rcsult is less than zero
2
3
Program Inten'uptions: None.
Load Multiple
LM RS 98
7 8 11 1 2 15 16 1 9 20 31
The set of general registers starting with the register
specified by RI and ending with the register specified
by Ra is loaded from the locations designated by the
second opcrand address.
The storage area from which the contents of the
general registers are obtained starts at the location
designated by the second operand address and con­
tinues through as many words as needed. The general
registers are loaded in the ascending order of their
addresses, starting with the register specified by RI and continuing up to and including the register speci­
fied by R a , with register 0 following register 15.
The second operand remains unchanged.
Condition Code: The code remains unchanged.
Program Interruptions:
Addressing
Specification