divide exception exists, and a program interruption
follows. In the case of a negative second operand, the
low-order part is in two's-complement notation.
Condition Code: The code remains unchanged.
Program Interruptions:
Addressing
Specification
Data
Fixed-point divide Convert to Decimal
eVD RX
4E
7 8 1 1 12 15 16 1 9 20 31
The radix of the first operand is changed from binary
to decimal, and the result is stored in the second op­
erand location. The number is treated as a right­
aligned signed integer both before and after con­
version.
The result is placed in the storage location desig­
nated by the second operand and has the packed
decimal format, as described in "Decimal Arithmetic." The result occupies a double-word in storage and must
be located on an integral boundary. The low-order
four bits of the field represent the sign. A positive sign
is encoded as 1100 or 1010; a negative sign is encoded
as 1101 or 1011. The choice between the two sign
representations is determined by the state of psw bit
12. The remaining 60 bits contain 15 binary-cod ed­
decimal digits in true notation.
The number to be converted is obtained as a 32-bit
signed integer from a general register. Since 15 deci­
mal digits are available for the decimal equivalent of
31 bits, an overflow cannot occur.
Condition Code: The code remains unchanged.
Resulting Condition Code: Protection Addressing
Specification Store 5T RX I 50 Rl
X
2
B2 D2 0 7 8 11 12 1516 1920 31
The first operand is stored at the second operand
location.
The 32 bits in the general register are placed un­
changed at the second operand location.
Condition Code: The code remains unchanged.
Program Interruptions: Protection Addressing
Specification Store Halfword
5TH RX 40 7 8 11 12 15 16 1 9 20 31
The first operand is stored at the halfword second
operand location.
The 16 low-order bits in the general register are
placed unchanged at the second operand location. The
16 high-order bits of the first operand do not partici­
pate and are not tested.
Condition Code: The code remains unchanged.
Program Interruptions: Protection Addressing
Specification Store Multiple 5TM R5 90 78 11 12 1516 1920
The set of general registers starting with the register
specified by Rl and ending with the register specified
by R3 is stored at the locations designated by the
second operand address.
The storage area where the contents of the general
registers are placed starts at the location designated
by the second operand address and continues through
as many words as needed. The general registers are
stored in the ascending order of their addresses, start­
ing with the register specified by Rl and continuing
up to and including the register specified by R
3
, with
register 0 following register 15. The first operands
remain unchanged.
Condition Code: The code remains unchanged. Program Interruptions: Protection Addressing S pecifica tion
Fixed-Point Arithmetic 31
Shift Left Single SLA RS 8B
7 8 11 12 1516 1920 31
The integer part of the first operand is shifted left the
number OIf bits specified by the second operand ad­
dress.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
The sign of the first operand remains unchanged. All
31 integer bits of the operand participate in the left
shift. Zeros are supplied to the vacated low-order reg­
ister positions.
If a bit unlike the sign bit is shifted out of position
1, an overflow occurs. The overflow causes a program
interruption when the fixed-point overflow mask bit
is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow Program Interruptions: Fixed-point overflow.
Programming Note
The base register participating in the generation of the
second operand address permits indirect specification
of the shift amount. A zero in the B:! field indicates
the absence of indirect shift specification.
Shift Right Single
SRA RS 8A
78 ]] 12 1516 1920 31
The integer part of the first operand is shifted right
the num her of bits specified by the second operand
address.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
The sign of the first operand remains unchanged.
All 31 integer bits of the operand participate in the
right shift. Bits equal to the sign are supplied to the
vacated high-order bit positions. Low-order bits are
shifted out without inspection and are lost.
32
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Program Interruptions: None.
Programming Note
Right-shifting is similar to division by powers of two
and to low-order truncation. Since negative numbers
are kept in two's-complement notation, truncation is
in the negative direction for both positive and nega­
tive numbers, rather than toward zero as in decimal
arithmetic. Shift amounts from 32 through 63 cause all signifi­
cant digits to be shifted out of the register. They give
a zero result for positive numbers and a minus one
result for negative numbers.
Shift Left Double
SLDA RS 8F
78 ]]/]2 1516 1920 31
The double-length integer part of the first operand is
shifted left the number of bits specified by the second
operand address.
The RL field of the instruction specifics an even/odd
pair of registers and must contain an even register
address. A specification exception occurs when Rl is
odd.
The second operand address is not used to address
data; its low-order 6-bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
The operand is treated as a number with 63 integer
bits and a sign in the sign position of the even register.
The sign remains unchanged. The high-order position
of the odd register contains an integer bit, and the
content of the odd register participates in the shift in the same manner as the other integer bits. Zeros are
supplied to the vacated low-order positions of the
registers.
If a bit unlike the sign bit is shifted out of bit posi­
tion 1 of the even register, an overflow occurs. The
overflow causes a program interruption when the fixed­
point overflow mask bit is one. Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow
Previous Page Next Page