acteristic is less than zero. The characteristic and
fraction are made zero, and a program interruption
occurs if the corresponding mask bit is one. Underflow
is not signaled when an operand's characteristics be­
come less than zero during prenormalization, and the
correct characteristic and fraction value are used in
the multiplication.
When all 14 result fraction digits are zero, the prod­
uct sign and characteristic are made zero, yielding a
true zero result without exponent underflow and ex­
ponent overflow causing a program interruption. The
program interruption for lost significance is never
taken for multiplication. Condit'ion Code: The code remains unchanged. Program Interruptions: Operation (if floating-point feature is not in-
stalled)
Addressing ( MD and ME only)
Specification
Exponent overflow
Exponent underflow
Programming Note
Interchanging the two operands in a floating-point
multiplication does not affect the value of the product.
Divide
DER RR. (Short Operands)
30
78 11 12 15
DE RX (Short Operands) I 70 Rl I X
2 I B2 0 7 8 11 12 1516 1920 31
DDR RR (Long Operands) I 20 Rl I R2 0 78 11 12 15
DD RX (Long Operands) I 60 Rl I X
2 I B2 0 7 8 11 12 1516 1920 31
48
The dividend (the first operand) is divided by the
divisor (the second operand) and replaced by the
quotient. No remainder is preserved.
In short-precision, the low-order halves of the float­
ing-point register are ignored and remain unchanged.
A floating-point division consists of a characteristic
subtraction and a fraction division. The difference be­
tween thc dividend and divisor characteristics plus
64 is used as an intermediate quotient characteristic.
The sign of the quotient is determined by the rules of
algebra.
The quotient fraction is normalized by prenormaliz­
ing the operands. Postnormalizing the intermediate
quotient is never necessary, but a right-shift may be
called for. The intermediate-quotient characteristic is
adjusted for the shifts. All dividend fraction digits
participate in forming the quotient, even if the normal­
ized dividend fraction is larger than the normalized
divisor fraction. The quotient fraction is truncated to
the desired number of digits.
A program interruption for exponent overflow oc­
curs when the final-quotient characteristic exceeds 127.
The operation is terminated.
A program interruption for exponent underflow oc­
curs if the final-quotient characteristic is less than
zero. The characteristic, sign, and fraction are made
zero, and the interruption occurs if the corresponding
mask bit is one. Underflow is not signaled for the
intermediate quotient or for the operand character­
istics during prenormalization.
When division by a divisor with zero fraction is at­
tempted, the opcration is suppressed. The dividend
remains unchanged, and a program interruption for
floating-point divide occurs. When the dividend frac­
tion is zero, the quotient fraction will be zero. The
quotient sign and characteristic are made zero, yield­
ing a true zero result without taking the program
interruption for exponent underflow and exponent
overflow. The program interruption for significance is
never taken for division.
Condition Code: The code remains unchanged. Program Interruptions: Operation (if floating-point feature is not in-
stalled)
Addressing (DD and DE only)
Specification
Exponent overflow
Exponent underflow
Floating-point divide
Store STE RX (Short Operands) I 70 R, I X
2 I B2 0 7 8 11 12 1516 1920 31 STD RX (Long Operands) I 60 R, I X
2 I B2 0 7 8 11 12 1516 1920 31
The first operand is stored at the second operand
location.
In short-precision, the low-order half of the first op­
erand register is ignored. The first operand remains
unchanged.
Condition Code: The code remains unchanged. Program Interruptions: Operation (if floating-point feature is not in-
stalled)
Addressing
Protection Specification Floating-Point Arithmetic Exceptions
Exceptional instructions, data, or results cause a pro­
gram interruption. When the interruption occurs, the
current psw is stored as an old psw, and a new psw
is obtained. The interruption code in the old psw iden­
tifies the cause of the interruption. The following ex­
ceptions cause a program interruption in floating-point
arithmetic.
Operation: The Floating-Point Feature is not in­
stalled, and an attempt is made to execute a floating­
point instruction. The instruction is suppressed. The
condition code and data in registers and storage re­
main unchanged. Protection: The storage key of a result location docs
not match the protection key in the psw. The opera­
tion is suppressed. Therefore, the condition code and
data in registers and storage remain unchanged.
Addressing: An address designates a location outside
the available storage for the installed system. The
operation is terminated. The result data and the con­
dition code, if affected, are unpredictable and should
not be used for further computation.
Specification: A short operand is not located on a
32-bit boundary or a long operand is not located on a
64-bit boundary; or, a floating-point register address
other than 0, 2, 4, or 6 is specified. The instruction is
suppressed. Therefore, the condition code and data
in registers and storage remain unchanged. The ad­
dress restrictions do not apply to the components from
which an address is generated -the content of the
D2 field and the contents of the registers specified by
X 2 and B 2 Exponent Overflow: The result exponent of an addi­
tion, subtraction, multiplication, or division overflows,
and the result fraction is not zero. The operation is
terminated; the result data are unpredictable and
should not be used for further computation. The con­
dition code is set to 3 for addition and subtraction and
remains unchanged for multiplication and division.
Exponent Underflow: The result of an addition, sub­
traction, multiplication, or division underflows, and the
result fraction is not zero. A program interruption oc­
curs if the exponent-underflow mask bit is one. The
operation is completed by replacing the result with
a true zero. The condition code is set to ° for addition
and subtraction and remains unchanged for multipli­
cation and division. The state of the mask hit does not
affect the result.
Significance: The result fraction of an addition or
subtraction is zero. A program interruption occurs if
the significance mask bit is one. The mask bit affects
also the result of the operation. When the significance
mask bit is a zero, the operation is completed by re­
placing the result with a true zero. When the signifi­
cance mask bit is one, the operation is completed
without further change to the characteristic of the
result. In either case, the condition code is set to 0. Floating-Point Divide: Division by a number with
zero fraction is attempted. The division is suppressed;
therefore, the condition code and data in registers and
storage remain unchanged.
Floating-Point Arithmetic 49
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