Store STE RX (Short Operands) I 70 R, I X
2I B2 0 7 8 11 12 1516 1920 31 STD RX (Long Operands) I 60 R, I X
2I B2 0 7 8 11 12 1516 1920 31
The first operand is stored at the second operand
location.
In short-precision, the low-order half of the first op
erand register is ignored. The first operand remains
unchanged.
Condition Code: The code remains unchanged.Program Interruptions: Operation (if floating-point feature is not in-
stalled)
Addressing
ProtectionSpecification Floating-Point Arithmetic Exceptions
Exceptional instructions, data, or results cause a pro
gram interruption. When the interruption occurs, the
current psw is stored as an old psw, and a new psw
is obtained. The interruption code in the old psw iden
tifies the cause of the interruption. The following ex
ceptions cause a program interruption in floating-point
arithmetic.
Operation: The Floating-Point Feature is not in
stalled, and an attempt is made to execute a floating
point instruction. The instruction is suppressed. The
condition code and data in registers and storage re
main unchanged.Protection: The storage key of a result location docs
not match the protection key in the psw. The opera
tion is suppressed. Therefore, the condition code and
data in registers and storage remain unchanged.
Addressing: An address designates a location outside
the available storage for the installed system. The
operation is terminated. The result data and the con
dition code, if affected, are unpredictable and should
not be used for further computation.
Specification: A short operand is not located on a
32-bit boundary or a long operand is not located on a
64-bit boundary; or, a floating-point register address
other than0, 2, 4, or 6 is specified. The instruction is
suppressed. Therefore, the condition code and data
in registers and storage remain unchanged. The ad
dress restrictions do not apply to the components from
which an address is generated -the content of the
D2 field and the contents of the registers specified by
X 2 andB 2 • Exponent Overflow: The result exponent of an addi
tion, subtraction, multiplication, or division overflows,
and the result fraction is not zero. The operation is
terminated; the result data are unpredictable and
should not be used for further computation. The con
dition code is set to 3 for addition and subtraction and
remains unchanged for multiplication and division.
ExponentUnderflow: The result of an addition, sub
traction, multiplication, or division underflows, and the
result fraction is not zero. A program interruption oc
curs if the exponent-underflow mask bit is one. The
operation is completed by replacing the result with
a true zero. The condition code is set to° for addition
and subtraction and remains unchanged for multipli
cation and division. The state of the mask hit does not
affect the result.
Significance: The result fraction of an addition or
subtraction is zero. A program interruption occurs if
the significance mask bit is one. The mask bit affects
also the result of the operation. When the significance
mask bit is a zero, the operation is completed by re
placing the result with a true zero. When the signifi
cance mask bit is one, the operation is completed
without further change to the characteristic of the
result. In either case, the condition code is set to0. Floating-Point Divide: Division by a number with
zero fraction is attempted. The division is suppressed;
therefore, the condition code and data in registers and
storage remain unchanged.
Floating-Point Arithmetic 49
2
2
The first operand is stored at the second operand
location.
In short-precision, the low-order half of the first op
erand register is ignored. The first operand remains
unchanged.
Condition Code: The code remains unchanged.
stalled)
Addressing
Protection
Exceptional instructions, data, or results cause a pro
gram interruption. When the interruption occurs, the
current psw is stored as an old psw, and a new psw
is obtained. The interruption code in the old psw iden
tifies the cause of the interruption. The following ex
ceptions cause a program interruption in floating-point
arithmetic.
Operation: The Floating-Point Feature is not in
stalled, and an attempt is made to execute a floating
point instruction. The instruction is suppressed. The
condition code and data in registers and storage re
main unchanged.
not match the protection key in the psw. The opera
tion is suppressed. Therefore, the condition code and
data in registers and storage remain unchanged.
Addressing: An address designates a location outside
the available storage for the installed system. The
operation is terminated. The result data and the con
dition code, if affected, are unpredictable and should
not be used for further computation.
Specification: A short operand is not located on a
32-bit boundary or a long operand is not located on a
64-bit boundary; or, a floating-point register address
other than
suppressed. Therefore, the condition code and data
in registers and storage remain unchanged. The ad
dress restrictions do not apply to the components from
which an address is generated -the content of the
D2 field and the contents of the registers specified by
X 2 and
tion, subtraction, multiplication, or division overflows,
and the result fraction is not zero. The operation is
terminated; the result data are unpredictable and
should not be used for further computation. The con
dition code is set to 3 for addition and subtraction and
remains unchanged for multiplication and division.
Exponent
traction, multiplication, or division underflows, and the
result fraction is not zero. A program interruption oc
curs if the exponent-underflow mask bit is one. The
operation is completed by replacing the result with
a true zero. The condition code is set to
and subtraction and remains unchanged for multipli
cation and division. The state of the mask hit does not
affect the result.
Significance: The result fraction of an addition or
subtraction is zero. A program interruption occurs if
the significance mask bit is one. The mask bit affects
also the result of the operation. When the significance
mask bit is a zero, the operation is completed by re
placing the result with a true zero. When the signifi
cance mask bit is one, the operation is completed
without further change to the characteristic of the
result. In either case, the condition code is set to
zero fraction is attempted. The division is suppressed;
therefore, the condition code and data in registers and
storage remain unchanged.
Floating-Point Arithmetic 49