Load Address
LARX 41
7 8 11 12 15 16 1920 31
The address of the second operand is inserted in the
low-order 24 bits of the general register specified byR i • The remaining bits of the general register are
made zero. No storage references for operands take
place.
The address specified by the X2, B2, and D2 fields is
inserted in bits 8-31 of the general register specified
byR i • Bits 0-7 are set to zero. The address is not in
spected for availability, protection, or resolution.
The address computation follows the rules for ad
dress arithmetic. Any carries beyond the 24th bit are
ignored.
Condition Code: The code remains unchanged.Program Interruptions: None.
Programming Note
The same general register may be specified by theRb X 2 , and H2 instruction field, except that general regis
ter0 can be specified only by the Ri field. In this
manner, it is possible to increment the low-order 24
bits of2l general register, other than 0, by the con
tents of the D2 field of the instruction. The register
to be incremented should be specified byRi and by
eitherX 2 (with B2 set to zero) or B2 (with X2 set to
zero ).Translah! TR S5 DC L
B1I B2 IU3J 78 15 16 19 20 31 32 35 36 . 47
The eight-bit bytes of the first operand are used as
arguments to reference the list designated by the sec
ond operand address. Each eight-bit function byte se
lected from the list replaces the corresponding argu
ment in the first operand.
The bytes of the first operand are selected one by
one for translation, proceeding left to right. Each
argument byte is added to the entire initial address,
the second operand address, in the low-order bit po
sitions. The sum is used as the address of the function
byte, which then replaces the original argument byte.
All data are valid. The operation proceeds until the
first operand field is exhausted. The list is not altered
unless an overlap occurs.
56
Condition Code: The code remains unchanged.Program Interruptions:
Protection
Addressing
Translate and Test
TRT55 DD
7 8
L
B1I B2 1516 1920 3132 3536 47
The eight-bit bytes of the first operand are used as
arguments to reference the list designated by the sec
ond' operand address. Each eight-bit function byte
thus selected from the list is used to determine the
continuation of the operation.vVhen the function byte
is a zero, the operation proceeds by fetching and
translating the next argument byte. When the function
byte is nonzero, the operation is completed by insert
ing the related argument address in general register
1, and by inserting the function byte in general regis
ter 2.
The bytes of the first operand are selected one by
one for translation, proceeding from left to right. The
first operand remains unchanged in storage. Fetching
of the function byte from the list is performed as in
TRANSLATE. The function byte retrieved from the list
is inspected for the all-zero combination.
When the function byte is zero, the operation pro
ceeds with the next operand byte. When the first op
erand field is exhausted before a nonzero function byte
is encountered, the operation is completed by setting
the condition code toO. The contents of general regis
ter 1 and 2 remain unchanged.
When the function byte is nonzero, the related ar
gument address is inserted in the low-order 24 bits of
general register 1. This address points to the argument
last translated. The high-order eight bits of register 1
remain unchanged. The function byte is inserted in
the low-order eight bits of general register 2. Bits0-23 of rcgister 2 remain unchanged. The condition code
is set to 1 when the one or more argument bytes have
not been translated. The condition code is set to 2 if
the last function byte is nonzero.
Resulting Condition Code:
o All function bytes are zero
1 Nonzero function byte before the first operand
field is exhausted
2 Last function byte is nonzero
3Program Interruptions:
Addressing
LA
7 8 11 12 15 16 19
The address of the second operand is inserted in the
low-order 24 bits of the general register specified by
made zero. No storage references for operands take
place.
The address specified by the X2, B2, and D2 fields is
inserted in bits 8-31 of the general register specified
by
spected for availability, protection, or resolution.
The address computation follows the rules for ad
dress arithmetic. Any carries beyond the 24th bit are
ignored.
Condition Code: The code remains unchanged.
Programming Note
The same general register may be specified by the
ter
manner, it is possible to increment the low-order 24
bits of
tents of the D2 field of the instruction. The register
to be incremented should be specified by
either
zero ).
B1
The eight-bit bytes of the first operand are used as
arguments to reference the list designated by the sec
ond operand address. Each eight-bit function byte se
lected from the list replaces the corresponding argu
ment in the first operand.
The bytes of the first operand are selected one by
one for translation, proceeding left to right. Each
argument byte is added to the entire initial address,
the second operand address, in the low-order bit po
sitions. The sum is used as the address of the function
byte, which then replaces the original argument byte.
All data are valid. The operation proceeds until the
first operand field is exhausted. The list is not altered
unless an overlap occurs.
56
Condition Code: The code remains unchanged.
Protection
Addressing
Translate and Test
TRT
7 8
L
B1
The eight-bit bytes of the first operand are used as
arguments to reference the list designated by the sec
ond' operand address. Each eight-bit function byte
thus selected from the list is used to determine the
continuation of the operation.
is a zero, the operation proceeds by fetching and
translating the next argument byte. When the function
byte is nonzero, the operation is completed by insert
ing the related argument address in general register
1, and by inserting the function byte in general regis
ter 2.
The bytes of the first operand are selected one by
one for translation, proceeding from left to right. The
first operand remains unchanged in storage. Fetching
of the function byte from the list is performed as in
TRANSLATE. The function byte retrieved from the list
is inspected for the all-zero combination.
When the function byte is zero, the operation pro
ceeds with the next operand byte. When the first op
erand field is exhausted before a nonzero function byte
is encountered, the operation is completed by setting
the condition code to
ter 1 and 2 remain unchanged.
When the function byte is nonzero, the related ar
gument address is inserted in the low-order 24 bits of
general register 1. This address points to the argument
last translated. The high-order eight bits of register 1
remain unchanged. The function byte is inserted in
the low-order eight bits of general register 2. Bits
is set to 1 when the one or more argument bytes have
not been translated. The condition code is set to 2 if
the last function byte is nonzero.
Resulting Condition Code:
o All function bytes are zero
1 Nonzero function byte before the first operand
field is exhausted
2 Last function byte is nonzero
3
Addressing