8e
7 8 11 12 1516
The double-length first operand is shifted right the
number of bits specified by the second operand ad
dress.
The R L field of the instruction specifies an even/odd
pair of registers and must contain an even register ad
dress. An odd value for Rl is a specification exception
and causes a program interruption. The second oper
and address is not used to address data; its low-order
six bits indicate the number of bit positions to be
shifted. The remainder of the address is ignored.
All 64 bits of the even/odd register pair specified
by Rl participate in the shift. Low-order bits are
shifted out of the odd-numbered register without in
spection and are lost. Zeros are supplied to the va
cated high-order positions of the registers.
Program Interruptions:
Programming Note
The logical shifts differ from the arithmetic shifts in
that the high-order bit participates in the shift and is
not propagated, the condition code is not changed,
and no overflow occurs.
Logical Operation Exceptions
Exceptional instructions, data,or results cause a pro
gram interruption. When the interruption occurs, the
current psw is stored as an old psw and a new psw
identifies the cause of the interruption. The following
exceptions cause a program interruption in logical op
erations.
Operation: The decimal feature is not installed, and
the instruction is EDIT or EDIT AND MARK. The opera
tion is suppressed. Therefore, the condition code and
data in registers and storage remain unchanged.
Protection: The storage key of a result location in
storage does not match the protection key in the psw.
The operation is suppressed. Therefore, the condition
code and data in registers and storage remain un
changed. The only exceptions are the variable-length
storage-to-storage operations, which are terminated.
For terminated operations, the result data and con
dition code, if affected, are unpredictable and should
not be used for further computation.
Addressing: An address designates a location out
side the available storage for the installed system. The
operation is terminated. The result data and the con
dition code, if affected, are unpredictable and should
not be used for further computation.
Specification: A fullword operand in a storage-to
register operation is not located on a 32-bit boundary
or an odd register address is specified for a pair of
general registers containing a 64-bit operand. The op
eration is suppressed. Therefore, the condition code
and data in registers and storage remain unchanged.
Data: A digit code of the second operand in EDIT or
EDIT AND MARK is invalid. The operation is terminated.
The result data and the condition code are unpredict
able and should not be used for further computation.
dress storage. Addresses used as a shift amount are
not tested. Similarly, the address generated by the use
of
do not apply to the components from which an ad
dress is generated -the contents of the Dl and D2
fields, and the contents of the registers specified by
X 2 , B1, and
2
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