Instructions are performed by the central process
ing unit primarily in the sequential order of their
locations. A departure from this normal sequential
operation may occur when branching is performed.
The branching instructions provide a means for mak
ing a two-way choice, to reference a subroutine, or to,repeat a segment of coding, such as a loop.
Branching is performed by introducing a branch ad
dress as a new instruction address.
The branch address may be obtained from one of
the general registers or it may be the address specified
by the instruction. The branch address is independent
of the updated instruction address.
The detailed operation of branching is determined
by the condition code which is part of the program
status word (psw) or by the results in the general reg
isters which are specified in the loop-closing opera
tions.
During a branching operation, the rightmost half of
the psw, including the updated instruction address,
may be stored before the instruction address is re
placed by the branch address. The stored information
may be used to link the new instruction sequence with
the preceding sequence.
The instruction EXECUTE is grouped with the branch
ing instructions. The branch address of EXECUTE desig
nates a single instruction to be inserted in the instruc
tion sequence. The updated instruction address norm
ally is not changed in this operation, and only the in
struction located at the branch address is executed.
All branching operations are provided in the stand
ard instruction set.
Normal Sequential Operation
Normally, operation of theCPU is controlled by in
structions taken in sequence. An instruction is fetched
from a location specified by the instruction-addressfield of the psw. The instruction address is increased
by the number of bytes of the instruction to address
the next instruction in sequence. This new instruction
address value, called the updated instruction address,
replaces the previous contents of the instruction-ad
dressfield in the psw. The current instruction is exe
cuted, and the same steps are repeated, using the up
dated instruction address to fetch the next instruction.
Branching
Instructions occupy a halfword or a multiple there
of. An instruction may have up to three halfwords.
The number of halfwords in an instruction is specified
by thefirst two instruction bits. A 00 code indicates a
halfword instruction, codes01 and 10 indicate a two
halfword instruction, and code 11 indicates a three
halfword instruction.
Hallword formatI OpCode o 78 15
Two-Ha/fword formatI Op Code
o
Three-Ha/fword formatI Op Code
BlI o 7 8 1516 1920 3132
Storage wraps around from the maximum address
able storage location, byte location 16,777,215, to byte
locationO. An instruction having its last halfword at
the maximum storage location is followed by the in
struction at addressO. Also, a multiple-halfword in
struction may straddle the upper storage boundary; no
special indication is given in these cases.
Conceptually, an instruction is fetched from storage
after the preceding operation is completed and before
execution of the current operation, even though physi
cal storage word size and overlap of instruction execu
tion with storage access may cause actual instruction
fetching to be different.
A change in the sequential operation may be caused
by branching, status-switching, interruption, or man
ual intervention. Sequential operation is initiated and
terminated from the system control panel.
Branching 61
ing unit primarily in the sequential order of their
locations. A departure from this normal sequential
operation may occur when branching is performed.
The branching instructions provide a means for mak
ing a two-way choice, to reference a subroutine, or to
Branching is performed by introducing a branch ad
dress as a new instruction address.
The branch address may be obtained from one of
the general registers or it may be the address specified
by the instruction. The branch address is independent
of the updated instruction address.
The detailed operation of branching is determined
by the condition code which is part of the program
status word (psw) or by the results in the general reg
isters which are specified in the loop-closing opera
tions.
During a branching operation, the rightmost half of
the psw, including the updated instruction address,
may be stored before the instruction address is re
placed by the branch address. The stored information
may be used to link the new instruction sequence with
the preceding sequence.
The instruction EXECUTE is grouped with the branch
ing instructions. The branch address of EXECUTE desig
nates a single instruction to be inserted in the instruc
tion sequence. The updated instruction address norm
ally is not changed in this operation, and only the in
struction located at the branch address is executed.
All branching operations are provided in the stand
ard instruction set.
Normal Sequential Operation
Normally, operation of the
structions taken in sequence. An instruction is fetched
from a location specified by the instruction-address
by the number of bytes of the instruction to address
the next instruction in sequence. This new instruction
address value, called the updated instruction address,
replaces the previous contents of the instruction-ad
dress
cuted, and the same steps are repeated, using the up
dated instruction address to fetch the next instruction.
Branching
Instructions occupy a halfword or a multiple there
of. An instruction may have up to three halfwords.
The number of halfwords in an instruction is specified
by the
halfword instruction, codes
halfword instruction, and code 11 indicates a three
halfword instruction.
Hallword format
Two-Ha/fword format
o
Three-Ha/fword format
Bl
Storage wraps around from the maximum address
able storage location, byte location 16,777,215, to byte
location
the maximum storage location is followed by the in
struction at address
struction may straddle the upper storage boundary; no
special indication is given in these cases.
Conceptually, an instruction is fetched from storage
after the preceding operation is completed and before
execution of the current operation, even though physi
cal storage word size and overlap of instruction execu
tion with storage access may cause actual instruction
fetching to be different.
A change in the sequential operation may be caused
by branching, status-switching, interruption, or man
ual intervention. Sequential operation is initiated and
terminated from the system control panel.
Branching 61