Programming Note
When all four mask bits are ones, the branch is un­
conditional. When all four mask bits are zero or when
the R2 field in the RR format contains zero, the branch
instruction is equivalent to a no-operation.
Branch all1d Link SALR 05 78 1112 15 SAL RX
45
7 8 11 12 15 16 19 20 31
The rightmost 32 bits of the PSW, including the up­
dated instruction address, are stored as link informa­
tion in the general register specified by R I . Subse­ quently, the instruction address is replaced by the
branch address.
The branch address is determined before the link
information is stored. The link information contains
the instruction length code, the condition code, and
the program mask bits, as well as the updated instruc­
tion address. The instruction-length code is 1 or 2,
depending on the format of the BRANCH AND LINK. Condition Code: The code remains unchanged.
Program Interruptions: None.
Programm.'ng Note
The link information is stored without branching when
in the RR format the R2 field contains zero.
When BRANCH AND LINK is the subject instruction of EXECUTE, the instruction-length code is 2.
Branch On Count SCTR RR 06 78 1112 15 SCT RX 46
7 8 11 12 15 16 19 20 31
The content of the general register specified by RI is
algebraically reduced by one. When the result is zero,
normal instruction sequencing proceeds with the up-
64
dated instruction address. When the result is not zero,
the instruction address is replaced by the branch ad­
dress.
The branch address is determined prior to the count­
ing operation. Counting does not change the condition
code. The overflow occurring on transition from the
maximum negative number to the maximum positive
number is ignored. Otherwise, the subtraction pro­
ceeds as in fixed-point arithmetic, and all 32 bits of the
general register participate in the operation.
Condition Code: The code remains unchanged.
Program Interruptions: None.
Programming Notes
Counting is performed without branching when the R2
field in the RR format contains zero.
An initial count of zero is not a special case. It re­
sults in minus one and causes branching to be exe­
cuted.
Branch On Index High
8XH RS 86
7 8 11 12 15 16 19 20 31
The second operand is added to the first operand', and
the sum is compared algebraically with the third op­
erand. Subsequently, the sum is placed in the first
operand location, regardless of whether the branch is
taken. When the sum is high, the instruction address
is replaced by the branch address. When the sum is
low or equal, instruction sequencing proceeds with the
updated instruction address.
The first and the second operands are in the registers
specified hy Rl and R 3 The third operand register ad­
dress is odd and is either one larger than R3 or equal
to R.'l' The branch address is determined prior to the
addition and comparison. Overflow caused by the addition is ignored and does
not affect the comparison. Otherwise, the addition and
comparison proceed as in fixed-point arithmetic. All
32 bits of the general registers participate in the opera­
tions, and negative quantities are expressed in two's­
complement notation. When the first and third oper­
and locations coincide, the original register contents
are used as third operand.
Condition Code: The code remains unchanged.
Program Interruptions: None.
Programming Note
The name "branch on index high" indicates that one
of the major purposes of this instruction is the incre-
menting and testing of an index value. The increment
may be algebraic and of any magnitude.
Branch On Index Low or Equal
BXLE RS 7 8 11 12 15 16 1 9 20 31
The second operand is added to the first operand, and
the sum is compared algebraically with the third op­
erand. Subsequently, the sum is placed in the first
operand location, regardless of whether the branch is
taken. When the sum is low or equal, the instruction
address is replaced by the branch address. When the
sum is high, normal instruction sequencing proceeds
with the updated instruction address.
The first and the second operands are in the registers
specified by Rl and Ri!' The third operand register ad­
dress is odd and is either one larger than R3 or equal
to Ri!. The branch address is determined prior to the
addition and comparison.
This instruction is similar to BRANCH ON INDEX HIGH,
except that the branch is successful when the sum is
low or equal compared to the third operand.
Condition Code: The code remains unchanged. Program Interruptions: None.
Execute
EX RX
44
7 8 11 12 15 16 19 20 31
The single instruction at the branch address is modi­
fied by the content of the general register specified by R" and the resulting subject instruction is executed.
Bits 8-15 of the instruction designated by the branch
address are oR'ed with bits 24-31 of the register speci­
fied by R1, except when register 0 is specified, which
indicates that no modification takes place. The sub­
ject instruction may be 16, 32, or 48 bits in length.
The oR'ing does not change either the content of the
register specified by R] or the instruction in storage
and is effective only for the interpretation of the in­
struction to be executed.
The execution and exception handling of the sub­
ject instruction are exactly as if the subject instruction
were obtained in normal sequential operation, except
for instruction address and instruction-length record­
ing.
The instruction address of the psw is increased by
the length of EXECUTE. This updated address and the
length code (2) of EXECUTE are stored in the psw in
the event of a branch-and-link subject instruction or
in the event of an interruption.
When the subject instruction is a successful branch­
ing instruction, the updated instruction address of the
psw is replaced by the branch address of the subject
instruction. When the subject instruction in turn is an EXECUTE, an execute exception occurs and results in a
program interruption. The effective address of EXE­ CUTE must be even; if not, a specification exception will
cause a program interruption.
Condition Code: The code may be set by the sub­
ject instruction. Program Interruptions:
Execute
Addressing
Specification
Programming Notes
The oR'ing of eight bits from the general register with
the designated instruction permits indirect length, in­
dex, mask, immediate data, and arithmetic-register
specification.
If the subject instruction is a successful branch, the
length code still stands at 2.
An addressing or specification exception may be
caused by EXECUTE or by the subject instruction.
Branching Exceptions
Exceptional instructions cause a program interrup­
tion. When the interruption occurs, the current psw is
stored as an old psw, and a new psw is obtained. The
interruption code in the old psw identifies the cause.
Exceptions that cause a program interruption in
branching are:
Execute: An EXECUTE instruction has as its subject
instruction another EXECUTE. Addressing: The branch address of EXECUTE desig­
nates an instruction-halfword location outside the
available storage for the particular installation.
Specification: The branch address of EXECUTE is odd.
The last three exceptions occur only for EXECUTE. The instruction is suppressed. Therefore, the condition
code and data in registers and storage remain un­
changed.
Exceptions arising for the subject instruction of EXE­ CUTE are the same as would have arisen had the sub­
ject instruction been in the normal instruction stream.
However, the instruction address stored in the old
Branching 65
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