Programming Note
When all four mask bits are ones, the branch is un
conditional. When all four mask bits are zero or when
the R2 field in the RR format contains zero, the branch
instruction is equivalent to a no-operation.
Branchall1d Link SALR 05 78 1112 15 SAL RX
45
7 8 11 12 15 16 1920 31
The rightmost 32 bits of thePSW, including the up
dated instruction address, are stored as link informa
tion in the general register specified byR I . Subse quently, the instruction address is replaced by the
branch address.
The branch address is determined before the link
information is stored. The link information contains
the instruction length code, the condition code, and
the program mask bits, as well as the updated instruc
tion address. The instruction-length code is 1 or 2,
depending on the format of the BRANCH AND LINK.Condition Code: The code remains unchanged.
Program Interruptions: None.
Programm.'ng Note
The link information is stored without branching when
in the RR format the R2 field contains zero.
When BRANCH AND LINK is the subject instruction ofEXECUTE, the instruction-length code is 2.
BranchOn Count SCTR RR 06 78 1112 15 SCT RX 46
7 8 11 12 15 16 1920 31
The content of the general register specified byRI is
algebraically reduced by one. When the result is zero,
normal instruction sequencing proceeds with the up-
64
dated instruction address. When the result is not zero,
the instruction address is replaced by the branch ad
dress.
The branch address is determined prior to the count
ing operation. Counting does not change the condition
code. The overflow occurring on transition from the
maximum negative number to the maximum positive
number is ignored. Otherwise, the subtraction pro
ceeds as in fixed-point arithmetic, and all 32 bits of the
general register participate in the operation.
Condition Code: The code remains unchanged.
Program Interruptions: None.
Programming Notes
Counting is performed without branching when the R2
field in the RR format contains zero.
An initial count of zero is not a special case. It re
sults in minus one and causes branching to be exe
cuted.
BranchOn Index High
8XHRS 86
7 8 11 12 15 16 1920 31
The second operand is added to the first operand', and
the sum is compared algebraically with the third op
erand. Subsequently, the sum is placed in the first
operand location, regardless of whether the branch is
taken. When the sum is high, the instruction address
is replaced by the branch address. When the sum is
low or equal, instruction sequencing proceeds with the
updated instruction address.
The first and the second operands are in the registers
specified hy Rl andR 3 • The third operand register ad
dress is odd and is either one larger than R3 or equal
toR.'l' The branch address is determined prior to the
addition and comparison.Overflow caused by the addition is ignored and does
not affect the comparison. Otherwise, the addition and
comparison proceed as in fixed-point arithmetic. All
32 bits of the general registers participate in the opera
tions, and negative quantities are expressed in two's
complement notation. When the first and third oper
and locations coincide, the original register contents
are used as third operand.
Condition Code: The code remains unchanged.
Program Interruptions: None.
Programming Note
The name"branch on index high" indicates that one
of the major purposes of this instruction is the incre-
When all four mask bits are ones, the branch is un
conditional. When all four mask bits are zero or when
the R2 field in the RR format contains zero, the branch
instruction is equivalent to a no-operation.
Branch
45
7 8 11 12 15 16 19
The rightmost 32 bits of the
dated instruction address, are stored as link informa
tion in the general register specified by
branch address.
The branch address is determined before the link
information is stored. The link information contains
the instruction length code, the condition code, and
the program mask bits, as well as the updated instruc
tion address. The instruction-length code is 1 or 2,
depending on the format of the BRANCH AND LINK.
Program Interruptions: None.
Programm.'ng Note
The link information is stored without branching when
in the RR format the R2 field contains zero.
When BRANCH AND LINK is the subject instruction of
Branch
7 8 11 12 15 16 19
The content of the general register specified by
algebraically reduced by one. When the result is zero,
normal instruction sequencing proceeds with the up-
64
dated instruction address. When the result is not zero,
the instruction address is replaced by the branch ad
dress.
The branch address is determined prior to the count
ing operation. Counting does not change the condition
code. The overflow occurring on transition from the
maximum negative number to the maximum positive
number is ignored. Otherwise, the subtraction pro
ceeds as in fixed-point arithmetic, and all 32 bits of the
general register participate in the operation.
Condition Code: The code remains unchanged.
Program Interruptions: None.
Programming Notes
Counting is performed without branching when the R2
field in the RR format contains zero.
An initial count of zero is not a special case. It re
sults in minus one and causes branching to be exe
cuted.
Branch
8XH
7 8 11 12 15 16 19
The second operand is added to the first operand', and
the sum is compared algebraically with the third op
erand. Subsequently, the sum is placed in the first
operand location, regardless of whether the branch is
taken. When the sum is high, the instruction address
is replaced by the branch address. When the sum is
low or equal, instruction sequencing proceeds with the
updated instruction address.
The first and the second operands are in the registers
specified hy Rl and
dress is odd and is either one larger than R3 or equal
to
addition and comparison.
not affect the comparison. Otherwise, the addition and
comparison proceed as in fixed-point arithmetic. All
32 bits of the general registers participate in the opera
tions, and negative quantities are expressed in two's
complement notation. When the first and third oper
and locations coincide, the original register contents
are used as third operand.
Condition Code: The code remains unchanged.
Program Interruptions: None.
Programming Note
The name
of the major purposes of this instruction is the incre-