menting and testing of an index value. The increment
may be algebraic and of any magnitude.
BranchOn Index Low or Equal
BXLERS 7 8 11 12 15 16 1 9 20 31
The second operand is added to the first operand, and
the sum is compared algebraically with the third op
erand. Subsequently, the sum is placed in the first
operand location, regardless of whether the branch is
taken. When the sum is low or equal, the instruction
address is replaced by the branch address. When the
sum is high, normal instruction sequencing proceeds
with the updated instruction address.
The first and the second operands are in the registers
specified by Rl andRi!' The third operand register ad
dress is odd and is either one larger than R3 or equal
toRi!. The branch address is determined prior to the
addition and comparison.
This instruction is similar toBRANCH ON INDEX HIGH,
except that the branch is successful when the sum is
low or equal compared to the third operand.
Condition Code: The code remains unchanged.Program Interruptions: None.
Execute
EX RX
44
7 8 11 12 15 16 1920 31
The single instruction at the branch address is modi
fied by the content of the general register specified byR" and the resulting subject instruction is executed.
Bits 8-15 of the instruction designated by the branch
address are oR'ed with bits 24-31 of the register speci
fied by R1, except when register0 is specified, which
indicates that no modification takes place. The sub
ject instruction may be 16, 32, or 48 bits in length.
The oR'ing does not change either the content of the
register specified by R] or the instruction in storage
and is effective only for the interpretation of the in
struction to be executed.
The execution and exception handling of the sub
ject instruction are exactly as if the subject instruction
were obtained in normal sequential operation, except
for instruction address and instruction-length record
ing.
The instruction address of the psw is increased by
the length ofEXECUTE. This updated address and the
length code (2) ofEXECUTE are stored in the psw in
the event of a branch-and-link subject instruction or
in the event of an interruption.
When the subject instruction is a successful branch
ing instruction, the updated instruction address of the
psw is replaced by the branch address of the subject
instruction. When the subject instruction in turn is anEXECUTE, an execute exception occurs and results in a
program interruption. The effective address of EXECUTE must be even; if not, a specification exception will
cause a program interruption.
Condition Code: The code may be set by the sub
ject instruction.Program Interruptions:
Execute
Addressing
Specification
Programming Notes
The oR'ing of eight bits from the general register with
the designated instruction permits indirect length, in
dex, mask, immediate data, and arithmetic-register
specification.
If the subject instruction is a successful branch, the
length code still stands at 2.
An addressing or specification exception may be
caused byEXECUTE or by the subject instruction.
Branching Exceptions
Exceptional instructions cause a program interrup
tion. When the interruption occurs, the current psw is
stored as an old psw, and a new psw is obtained. The
interruption code in the old psw identifies the cause.
Exceptions that cause a program interruption in
branching are:
Execute: AnEXECUTE instruction has as its subject
instruction anotherEXECUTE. Addressing: The branch address of EXECUTE desig
nates an instruction-halfword location outside the
available storage for the particular installation.
Specification: The branch address ofEXECUTE is odd.
The last three exceptions occur only forEXECUTE. The instruction is suppressed. Therefore, the condition
code and data in registers and storage remain un
changed.
Exceptions arising for the subject instruction of EXECUTE are the same as would have arisen had the sub
ject instruction been in the normal instruction stream.
However, the instruction address stored in the old
Branching 65
may be algebraic and of any magnitude.
Branch
BXLE
The second operand is added to the first operand, and
the sum is compared algebraically with the third op
erand. Subsequently, the sum is placed in the first
operand location, regardless of whether the branch is
taken. When the sum is low or equal, the instruction
address is replaced by the branch address. When the
sum is high, normal instruction sequencing proceeds
with the updated instruction address.
The first and the second operands are in the registers
specified by Rl and
dress is odd and is either one larger than R3 or equal
to
addition and comparison.
This instruction is similar to
except that the branch is successful when the sum is
low or equal compared to the third operand.
Condition Code: The code remains unchanged.
Execute
EX RX
44
7 8 11 12 15 16 19
The single instruction at the branch address is modi
fied by the content of the general register specified by
Bits 8-15 of the instruction designated by the branch
address are oR'ed with bits 24-31 of the register speci
fied by R1, except when register
indicates that no modification takes place. The sub
ject instruction may be 16, 32, or 48 bits in length.
The oR'ing does not change either the content of the
register specified by R] or the instruction in storage
and is effective only for the interpretation of the in
struction to be executed.
The execution and exception handling of the sub
ject instruction are exactly as if the subject instruction
were obtained in normal sequential operation, except
for instruction address and instruction-length record
ing.
The instruction address of the psw is increased by
the length of
length code (2) of
the event of a branch-and-link subject instruction or
in the event of an interruption.
When the subject instruction is a successful branch
ing instruction, the updated instruction address of the
psw is replaced by the branch address of the subject
instruction. When the subject instruction in turn is an
program interruption. The effective address of EXE
cause a program interruption.
Condition Code: The code may be set by the sub
ject instruction.
Execute
Addressing
Specification
Programming Notes
The oR'ing of eight bits from the general register with
the designated instruction permits indirect length, in
dex, mask, immediate data, and arithmetic-register
specification.
If the subject instruction is a successful branch, the
length code still stands at 2.
An addressing or specification exception may be
caused by
Branching Exceptions
Exceptional instructions cause a program interrup
tion. When the interruption occurs, the current psw is
stored as an old psw, and a new psw is obtained. The
interruption code in the old psw identifies the cause.
Exceptions that cause a program interruption in
branching are:
Execute: An
instruction another
nates an instruction-halfword location outside the
available storage for the particular installation.
Specification: The branch address of
The last three exceptions occur only for
code and data in registers and storage remain un
changed.
Exceptions arising for the subject instruction of EXE
ject instruction been in the normal instruction stream.
However, the instruction address stored in the old
Branching 65
