running state may be achieved by the privileged in
structionLOAD psw, by an interruption such as for SUPERVISOR CALL, or by initial program loading. Switch
ing from the wait state may be achieved by anI/O or
external interruption or, again, by initial program
loading. The new psw may introduce the wait or run
ning state regardless of the preceding state. No ex
plicit operator control is provided for changing the
wait state.
Timer updating is not affected by the choice be
tween running and wait state.
Programming Note
To leave the wait state without manual intervention,
theCPU should remain interruptable for some active I/O or external interruption source.
Masked States
TheCPU may be masked or interruptable for all sys
tems and machine-check interruptions and for some
program interruptions. When theCPU is interruptable
for a class of interruptions, these interruptions are
accepted. When theCPU is masked, the system inter
ruptions remain pending, while the program and ma
chine-check interruptions are ignored.
The system mask bits (psw bits0-7), the program
mask bits (psw bits 36-39), and the machine-check
mask bit (psw bit 13) indicate as a group the masked
state of theCPU. When a mask bit is one, the CPU is
interruptible for the corresponding interruptions.
When the mask bit is zero, these interruptions are
masked off. The system mask bits indicate the masked
state of theCPU for the multiplexor channel, the six
selector channels, and the external signals. The pro
gram mask bits indicate the masked state for four of
the 15 types of program exceptions. The machine
check mask bit pertains to all machine checks.Pro gram interruptions not maskable, as well as the super
visor-call interruption, are always taken. The masked
states are not indicated on the operator sections of the
system control panel.
"Most mask bits do not affect the execution ofCPU operations. The only exception is the significance mask
bit, which determines the manner in which a Hoating
point operation is completed when a significance ex
ception occurs.
The interruptable state of theCPU is switched by
changing the mask bits in the psw. The program mask
may be changed separately bySET PROGRAM MASK, and
the system mask may be changed separately by the
privileged instructionSET SYSTEM MASK. The machine
check mask bit can be changed only by introducing an
entire newPSW, as is the case with the problem-state
and wait-state bits. Thus, a change in the entire
68
masked status may be achieved by the privileged in
structionLOAD psw, by an interruption such as for sup ERVISOR CALL, or by initial program loading. The new
psw may introduce a new masked state regardless of
the preceding state. No explicit operator control is
provided for changing the masked state.
Timer updating is not affected by the choice be
tween masked or interruptable states.
Programming Note
To prevent an interruption-handling routine from being interrupted before necessary housekeeping steps
are performed, the new psw for that interruption
should mask theCPU for further interruptions of the
kind that caused the interruption.
Stopped State
When theCPU is in the stopped state, instructions and
interruptions are not executed. In the operating state,
theCPU executes instructions (if not waiting) and in
telTui1tions(if not masked off).
The stopped state is indicated on the operator con
trol section of the system control panel by the manual
light. The stopped state is not identified by a bit in
the psw.
Achange in the stopped or operating state can be
effected only by manual intervention or by machine
malfunction. No instructions or interruptions can stop
or start theCPU. The CPU is commanded to stop when
the stop key on the operator intervention section of
the system control panel is pressed, when an address
comparison indicates equality, and when the rate
switch is set toINSTRUCTION STEP. In addition, the CPU is placed in the stopped state after power is turned on
or following a system reset, except during initial pro
gram loading. TheCPU is placed in the operating state
when the start key on the operator intervention panel
is pressed. TheCPU is also placed in the operating
state when initial program loading is commenced.
The transition from operating to stopped state oc
curs at the end of instruction execution and prior to
starting the next instruction execution. When theCPU is in the wait state, the transition takes place immedi
ately. All interruptions pending and not masked off
are taken while theCPU is still in the operating state.
They cause an old psw to be stored and a new psw to
be fetched before entering the stopped state.Once the CPU is in the stopped state, interruptions are no longer
takcn but remain pending.
The timer is not updated in the stopped state.
Programming Notes
Except for timing considerations, execution of a pro
gram is not affected by stopping theCPU.
struction
ing from the wait state may be achieved by an
external interruption or, again, by initial program
loading. The new psw may introduce the wait or run
ning state regardless of the preceding state. No ex
plicit operator control is provided for changing the
wait state.
Timer updating is not affected by the choice be
tween running and wait state.
Programming Note
To leave the wait state without manual intervention,
the
Masked States
The
tems and machine-check interruptions and for some
program interruptions. When the
for a class of interruptions, these interruptions are
accepted. When the
ruptions remain pending, while the program and ma
chine-check interruptions are ignored.
The system mask bits (psw bits
mask bits (psw bits 36-39), and the machine-check
mask bit (psw bit 13) indicate as a group the masked
state of the
interruptible for the corresponding interruptions.
When the mask bit is zero, these interruptions are
masked off. The system mask bits indicate the masked
state of the
selector channels, and the external signals. The pro
gram mask bits indicate the masked state for four of
the 15 types of program exceptions. The machine
check mask bit pertains to all machine checks.
visor-call interruption, are always taken. The masked
states are not indicated on the operator sections of the
system control panel.
"Most mask bits do not affect the execution of
bit, which determines the manner in which a Hoating
point operation is completed when a significance ex
ception occurs.
The interruptable state of the
changing the mask bits in the psw. The program mask
may be changed separately by
the system mask may be changed separately by the
privileged instruction
check mask bit can be changed only by introducing an
entire new
and wait-state bits. Thus, a change in the entire
68
masked status may be achieved by the privileged in
struction
psw may introduce a new masked state regardless of
the preceding state. No explicit operator control is
provided for changing the masked state.
Timer updating is not affected by the choice be
tween masked or interruptable states.
Programming Note
To prevent an interruption-handling routine from be
are performed, the new psw for that interruption
should mask the
kind that caused the interruption.
Stopped State
When the
interruptions are not executed. In the operating state,
the
telTui1tions
The stopped state is indicated on the operator con
trol section of the system control panel by the manual
light. The stopped state is not identified by a bit in
the psw.
A
effected only by manual intervention or by machine
malfunction. No instructions or interruptions can stop
or start the
the stop key on the operator intervention section of
the system control panel is pressed, when an address
comparison indicates equality, and when the rate
switch is set to
or following a system reset, except during initial pro
gram loading. The
when the start key on the operator intervention panel
is pressed. The
state when initial program loading is commenced.
The transition from operating to stopped state oc
curs at the end of instruction execution and prior to
starting the next instruction execution. When the
ately. All interruptions pending and not masked off
are taken while the
They cause an old psw to be stored and a new psw to
be fetched before entering the stopped state.
takcn but remain pending.
The timer is not updated in the stopped state.
Programming Notes
Except for timing considerations, execution of a pro
gram is not affected by stopping the