When because of machine malfunction the CPU is
unable to end an instruction, the stop key is not effect­
ive, and initial program loading or system reset should
be used.
Input/output operations continue to completion
while the CPU is in the problem, wait, masked, or
stopped state. However, no new I/O operations can be
initiated while the CPU is stopped, waiting, or in the
problem state. Also, the interruption caused by I/O completion remains pending when masked off or when
the CPU is in the stopped state.
Storage Protection Storage protection is provided to protect the contents
of certain areas of storage from destruction caused by
erroneous storing of information during the execution
of a program. This protection is achieved by identify­
ing blocks of storage with a storage key and compar­
ing this key with a protection key supplied with the
data to be stored. The detection of a mismatch is a
protection exception and results in a program inter­
ruption.
Area Identification
For protection purposes, main storage is divided into
blocks of 2,048 bytes, each block having an address
that is a multiple of 2,048. A four-bit storage key is
associated with each block. When data are stored in a
storage block, the storage key is compared with the
protection key. The protection key of the current psw
is used as the comparand when storing is specified by
an instruction. When storing is specified by a channel
operation, the protection key supplied to the channel
by the command address word is used as the com­
parand. The keys are said to match when they are
equal or when either one is zero.
The storage key is not part of addressable storage.
The key is changed by SET STORAGE KEY and is in­
spected by INSERT STORAGE KEY. The protection key in
the psw occupies bits 8-11 of that control word. The
protcction key of a channel is recorded in bits 0-3 of
the channel status word, which is stored as a result of
the channel operation.
Protection Action
The storage-protection system is always active. It is
independent of the problem, supervisor, or masked
state of the CPU and of the type of instruction or I/O command being executed.
When an instruction causes a protection mismatch,
execution of the instruction is suppressed or termi­
nated, and program execution is altered by a program
interruption. The protected storage location always
remains unchanged.
In general, the detection of a protected location
causes the instruction specifying this location to be
suppressed, that is to be omitted entirely. In opera­
tions using multiple words or variable-length fields,
part of the operation may already have been com­
pleted when the protected area is referenced. In these
operations the instruction cannot be suppressed and,
hence, is terminated. Protection mismatch due to an I/O operation causes
data transmission to be terminated in such a way that
the protected storage location remains unchanged.
The mismatch is indicated in the channel status word
stored as a result of the operation. Storage protection is optional in some models. When
protection is not installed, the protection key in the
psw and the protection key of the channels must be
zero; otherwise, a program interruption or program­
check I/O termination occurs.
Locations Protected
All main-storage locations where information is stored
in the course of an operation are subject to protection.
A location not actually used does not cause protection
action.
Locations whose addresses are generated by the CPU for updating or interruption purposes, such as the
timer, channel status word, or psw addresses, are not
protected. However, when the program specifies these
locations, they are subject to protection.
Program Status Word
The psw contains all information not contained in
storage or registers but required for proper program
execution. By storing the PSW, the program can pre­
serve the detailed status of the CPU for subsequent in­ spection. By loading a new psw or part of a PSW, the
state of the CPU may be changed.
In certain circumstances all of the psw is . . _ .0d or
loaded; in others, only part of it. The entire psw is
stored, and a new psw is introduced when the CPU is
interrupted. The rightmost 32 bits are stored in BRANCH AND LINK. The LOAD PSW introduces a new PSW; SET PROGRAM mask introduces a new condition
code and program-mask field in the psw; SET SYSTEM MASK introduces a new system-mask field.
The psw has the following format: Program Status Word
System Mask Interrupti on Code 31 Instruction Address
32 33 34 35 36 39 40 63 Status Switching 69

The following is a summary of the purposes of the
psw fields: System Mask: Bits 0-7 of the psw are associated with I/O channels and external signals as specified in the
following table. When a mask bit is one, thc source
can interrupt the cpu. When a mask bit is zero, the
corresponding source can not interrupt the cpu and
interruptions remain pending. SYSTEM MASK HIT o
1
2
3
4
5 6 7
7
7 INTERRUPTION SOURCE Multiplexor channel
Selector channel 1
Selector channel 2
Selector channel 3
Selector channel 4
Selector channel 5
Selector channel 6 Timer
Interrupt key
External signal Protection Key: Bits 8-11 of the psw form the cpu
protection key. The key is matched with a storage key
whenever a result is stored. When the protection fea­
ture is not implemented, bits 8-11 must be zero when
loaded and are zero when stored.
ASCII(A): When bit 12 of the psw is one, the codes
preferred for the extended ASCII code are generated
for decimal results. When psw 12 is zero, the codes
preferred for the extended binary-coded-decimal inter­
change code are generated.
Machine-Check Mask (M): When psw bit 13 is one,
the machine-check interruption, machine check out­
signal, and diagnostics occur upon malfunction detec­
tion. When bit 13 of the psw is zero, the cpu is masked
for machine-check interruptions, and any associated
signals and diagnostic procedures do not take place.
The interruption does not remain pending.
Wait State (W): ""hen bit 14 of the psw is one, the
cpu is in the wait state. When psw bit 14 is zero, the
cpu is in the running state. Problem State (P): When bit 15 of the psw is one,
the cpu is in the problem state. When psw bit 15 is
zero, the cpu is in the supervisor state.
Interruption Code: Bits 16-31 of the psw identify
the cause of an I/O, program, supervisor call, or ex­
ternal interruption. The code is zero when a machine­
check interruption occurs. Use of the code for all five interruption types is shown in a table appearing
in the "Interruptions" section.
Instruction Length Code (ILC): The code in psw
bits 32 and 33 indicates the length, in halfwords, of the
last-interpreted instruction when a program or super­
visor-call interruption occurs. The code is unpredict­
able for I/O, external, or machine-check interruptions.
Encoding of these bits is summarized in a table ap­
pearing in the "Interruptions" sections. 70 Condition Code (CC): Bits 34 and 35 of the psw are
the two bits of the condition code. The condition
codes for all instructions arc summarized in a table
appearing in the "Branching" section. Program Mask: Bits 36-39 of the psw are the four
program mask bits. Each bit is associated with a pro­ gram exception, as specified in the following table.
When the mask bit is one, the exception results in an
interruption. When the mask bit is zero, no interrup­
tion occurs. The significance mask bit also detennines
the manner in which Hoating-point addition and sub­
traction are completed. PROGRAM MASK BIT PROGHAM EXCEPTION
36 Fixed-point overflow
37 Decimal overflow
38 Exponent underflow
39 Significance
Instruction Address: Bits 40-63 of the psw are the in­
struction address. This address specifies the leftmost
eight-bit byte position of the next instruction.
Multisystem Operation
Various fcatures are provided to permit communica­
tion between individual systems. Messages may be
transmitted by means of a shared I/O device, a chan­
nel connector, or a shared storage unit. Signaling may
be accomplished when the direct control feature is in­
stalled by WRITE DIRECT and READ DIRECI' and by the
signal-in lines of the external interruption.
The multisystem feature adds to these facilities the
ability to relocate direct addressed locations, to signal
the machine malfunction of one system to another,
and to initiate system operation from another system.
Direct Address Relocation
Addresses 0-4095 can be generated without a base
address or index. This property is important when the
psw and general register contents must be preserved
and restored during program-switching. These ad­
dresses further include all addresses generated by the
cpu for fixed locations, such as old PSW, new psw,
channel address word, channel status word, and timer.
This set of addresses can be relocated by means of a
main prefix to permit more than one cpu to use one
uniquely addressed storage. Furthermore, an alternate prefix is provided to permit a change in relocation in
case storage malfunction occurs or reconfiguration be­
comes otherwise desirable.
A prefix is used whenever an address has the high­
order 12 bits all-zero. The use of the prefix is inde­
pendent of the manner in which the address is gener­
ated and does not apply to the components, such as the