The program may have zeros in the base address,
index, or displacement fields. A zero is used to indi­
cate the absence of the corresponding address com­
ponent. A base or index of zero implies that a zero
quantity is to be used in forming the address, regard­
less of the contents of general register O. A displace­
ment of zero has no special significance. Initialization,
modification, and testing of base addresses and in­
dexes can be carried out by fixed-point instructions,
As an aid in describing the logic of the instruction
format, examples of two instructions and their related
instruction formats follow. RR Format I Add 7 9
o 78 1112 15
Execution of the ADD instruction adds the contents of
general register 9 to the contents of general register
7 and the sum of the addition is placed in general
register 7.
RX Format
Store 3 10 14 300 7 8 11 1 2 15 16 1 9 20 31
Execution of the STORE instruction stores the contents
of general register 3 at a main-storage location ad­
dressed by the sum of 300 and the low-order 24 bits
of general registers 14 and 10. Sequential Instruction Execution
Normally, the operation of the CPU is controlled by
instructions taken in sequence. An instruction is
fetched from a location specified by the current in­
struction address. The instruction address is then in­
creased by the number of bytes in the instruction to
address the next instruction in sequence. The instruc­
tion is then executed and the same steps are repeated
using the new value of the instruction address.
Conceptually, all halfwords of an instruction are
fetched from storage after the preceding operation is
completed and before execution of the current oper­
ation, even though physical storage word size and
overlap of instruction execution with storage access
may cause actual instruction fetching to be different.
Thus, it is possible to modify an instruction in storage
by the immediately preceding instruction.
A change from sequential operation may be caused
by branching, status switching, interruptions, or man­
ual intervention.
The normal sequence of instructions is changed when
reference is made to a subroutine, when a two-way
choice is encountered, or when a segment of coding,
such as a loop, is to be repeated. All these tasks can
be accomplished with branching instructions.
Subroutine linkage permits not only the intro­
duction of a new instruction address but also the pres­
ervation of the return address and associated informa­
Decision-making is generally and symmetrically
provided by the BRANCH ON CONDITION instruction.
This instruction inspects a two-bit condition code that
reflects the result of a majority of the arithmetic, logi­
cal, and I/O operations. Each of these operations can
set the code in anyone of four states, and the con­
ditional branch can specify any selection of these four
states as the criterion for branching. For example, the
condition code reflects such conditions as nonzero,
first operand high, equal, overflow, channel busy, zero,
etc. Once set, the condition code remains unchanged
until modified by an instruction that reflects a dif­
ferent condition code.
The two bits of the condition code provide for four
possible condition code settings: 0, 1, 2, and 3. The
specific meaning of any setting is significant only to
the operation setting the condition code.
Loop control can be performed by the conditional
branch when it tests the outcome of address arith­
metic and counting operations. For some particularly
frequent combinations of arithmetic and tests, the in­
provided. These branches, being specialized, provide
increased performance for these tasks.
Program Status Word
A double word, the program status word (psw), con­
tains the information required for proper program
execution. The psw includes the instruction address,
condition code, and other fields to be discussed. In
general, the psw is used to control instruction se­
quencing and to hold and indicate the status of the
system in relation to the program being executed. The
active or controlling psw is called the "current psw." By storing the current psw during an interruption, the
status of the CPU can be preserved for subsequent in­
spection. By loading a new psw or part of a psw, the
state of the CPU can be initialized or changed. Figure
14 shows the psw format.
System Structure 15
0-7 System mask
o Multiplexor channel mask
1 Selector c:hannel 1 mask
2 Selector c:hannel 2 mask
3 Selector channel 3 mask
4 Selector c:hannel 4 mask
5 Selector c:hannel 5 mask
6 Selector c:hannel 6 mask
7 External mask
8-11 Protection key
12 ASCII mode (A)
13 Machine check mask (M)
14 Wait state (W)
15 Problem state (P)
16-31 Interruption code
32-33 Instruction Length code (ILC) 34-35 Condition code (CC)
36-39 Program mask
36 Fixed-point overflow mask
37 Decimal overflow mask
38 Exponent underflow mask
39 Significance mask 40-63 Instruction address
Figure 14. Program Status Word Format The interruption system permits the CPU to change
state as a result of conditions external to the system,
in input/output (I/O) units or in the CPU itself. Five
classes of interruption conditions are possible: I/O, program, supervisor call, external, and machine check.
Each class has two related psw's called "old" and "new" in unique main-storage locations (Figure 15).
In all classes, an interruption involves merely storing
the current psw in its "old" position and making the
psw at the "new" position the current psw. The "old" psw holds all necessary status information of the sys­ tem existing at the time of the interruption. If, at the
conclusion of the interruption routine, there is an in­ struction to make the old psw the current psw, the
system is lrestored to the state prior to the interruption
and the interrupted routine continues.
Address length Purpose
o 0000 0000 double word Initial program loading PSW 8 0000 1000 double word Initial program loading CCWI 16 0001 0000 double word Initial program loading CCW2 24 0001 1000 double word External old PSW 32 0010 0000 double word Supervisor call old PSW 40 0010 1000 double word Program old PSW 48 0011 0000 double word Machine check old PSW 56 0011 1000 double word Input/output old PSW 64 0100 0000 double word Channel status word
72 0100 1000 word Channel address word
76 0100 1100 word Unused 80 0101 0000 word Timer
84 0101 0100 word Unused
88 0101 1000 double word External new PSW 96 0110 0000 double word Supervisor call new PSW 1 04 011 a 1000 double word Program new PSW 112 0111 0000 double word Machine check new PSW 120 0111 1000 double word Input/output new PSW 128 1000 0000 Diagnostic scan-out area *
* The size of j,he diagnostic scan-out area depends upon the
particular system's CPU and I/O channels. Figure 15. Permanent Storage Assignments
Interruptions are taken only when the CPU is inter­
ruptable for the interruption source. The system mask,
program mask, and machine check mask bits in the
psw may be used to mask certain interruptions. When
masked off, an interruption either remains pending or
is ignored. The system mask may keep I/O and ex­ ternal interruptions pending, the program mask may
cause four of the 15 program interruptions to be ig­ nored, and the machine-check mask may cause ma­ chine-check interruptions to be ignored. Other inter­ ruptions cannot be masked off.
An interruption always takes place after one in­ struction execution is finished and before a new in­ struction execution is started. However, the occurence
of an interruption may affect the execution of the cur­ rent instruction. To permit proper programmed action
following an interruption, the cause of the interrupt­
ion is identified and provision is made to locate the
last executed instruction. Input /OutPIJt Interruption
An I/O interruption provides a means by which the CPU responds to conditions in the channels and I/O units.
An I/O interruption can occur only when the related
channel is not masked. The address of the channel
and I/O unit involved are recorded in the old psw.
Further information concerning the I/O action is pre­ served in the channel status word (csw) that is stored
during the interruption.
Program Interruption
Unusual conditions encountered in a program create
program interruptions. These conditions include in­ correct operands and operand specifications, as well
as exceptional results. The interruption code identifies
the interruption cause. Figure 16 shows the different
causes that may occur.
Interruption Program Interrupti on
Code Cause
1 00000001 Operation
2 00000010 Privileged operation
3 00000011 Execute
4 00000100 Protection 5 00000101 Addressing
6 00000110 Specification
7 00000111 Date
8 00001000 Fixed-point overflow
9 00001001 Fixed-point divide 10 00001010 Decimal overflow
11 0000101 I Decimal divide
12 00001100 Exponent overflow
13 000011 01 Exponent underflow
14 00001 110 Significance
15 00001111 Floating-point divide
Figure 16. Interruption Code for Program Interruption
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