Bit Positions ---- •• 76
L I X5 00------, 4321 00 01 10 11 01 00 01 10 11 00 01 10 ..----10-------.1 '--1 ----11-------. 11 00 01 10 11 0000 NULL DCa b a
blank (a) P 0001 50M DC
1 --- ,---- ----- - r----
--- --- Q a q 0010 EOA DC
2 0011 EOM DC
2 41= 3
B R C 5
b r I---+----t-------f -------- C S -- 1------+----+ 0100 EOT DC4 5TOP $ 4 D T d t 0101 WRU ERR % 5 E U
e u --- ---- ----- 1---- -- -- - f-------f----J-----j 0110 RU 5YNC & 6 F V v 0111 BELL LEM -- ,------ ----"- ,
7 - f--- G W - --- - -- - ------- 9 W 1000 BK5P 50 1001 HT 51
H X --f-- - I Y f----- h x ---- 1----:- - - ---- I Y - I-- -- -----f-----, 1010 LF 52 J Z i z r------ ------+----__j --- 1011 VT 53 + K [ k 1100 FF 54 ---- L " r--·--r---+--1-- 1101 CR 55 M ::J m 1110 50 56 N
f r----- r- - -f- -- - ---
n E5C 1--- r- -- - - --1--- -I ---------- 1111 51 57 / ? 0 4-- o DEL
Figure 12. Eight-Bit Representation for American Standard Code for Information Interchange
for Use in Eight-Bit Environment
ter-to-storage operation; SI, a storage and immediate­
operand operation; and SS, a storage-to-storage oper­
For purposes of describing the execution of instruc­
tions, operands are designated as first and second op­ erands and, in the case of BRANCH ON INDEX, third op­
erands. These names refer to the manner in which the
operands participate. The operand to which a field in
an instruction format applies is generally denoted by
the number following the code name of the field, for
example, Rl, Bl, L 2 , D 2 In each format, the first instruction halfword con­
sists of two parts. The first byte contains the oper­
ation code (op code). The length and format of an
instruction are specified by the first two bits of the
operation code.
10 Two halfwords RS or SI 11 Three halfwords SS The second byte is used either as two 4-bit fields
or as a single eight-bit field. This byte can contain the
following information:
Four-bit operand register specification Rb R 2 , or
R 3 )
Four-bit index register specification (X2)
Four-bit mask (M1)
Four-bit operand length specification (Ll or L2)
Eight-bit operand length specification (L)
Eight-bit byte of immediate data (12)
In some instructions a four-bit field or the whole sec­
ond byte of the first halfword is ignored.
The second and third halfwords always have the
same format:
Four-bit base register designator (Bl or B2), fol­ lowed by a 12-bit displacement (Dl or D2)'
Address Generation
For addressing purposes, operands can be grouped
in three classes: explicitly addressed operands in main
storage, immediate operands placed as part of the in- System Structure 13
L- ____ F_ir_s.t __ ______ -; ____ s_ec_o_n_d __ ________ r Byte' Byte 2 I :0 1 I I I 10 I I Register Register Operand' Operand 2 Op Code I R 1 I R2 I RR Format
7 8 11 12 15 1 Register Operand' Op Code I R, I X, B2
7 8 11 12 1516 I I I Register Register Operand' Operand 3 r---' ..---A-----y 7 8 I 11 12 Immediate Op Code 12 1516 I 78 1516 I 1 I I 1920 1920 1920 Address Operand 2 " D2
Address ___ _
Address Oper?nd 1
31 1 I I RX Format
RS Format SI Format I Length I Address Address ____ __ SS Format Op Code I L, I L2 I B, D,
7 8 11 12 15 16 1920 ------.-31-'--------1----------------'47 Figure 13. Five Basic Instruction Formats
struction stream in main storage, and operands lo­
cated in the general or floating-point registers.
To permit the ready relocation of program seg­
ments and to provide for the flexible specifications of
input, output, and working areas, all instructions re­
ferring to main storage have been given the capacity
of employing a full address.
The address used to refer to main storage is gen­
erated from the following three binary numbers:
Base Address (B) is a 24-bit number contained in a
general register specified by the program in the B
field of the instruction. The B field is included in
every address specification. The base address can be
used as a means of static relocation of programs and
data. In array-type calculations, it can specify the lo­
cation of an array and, in record-type processing, it
can identify the record. The base address provides for
addressing the entire main storage. The base address
may also be used for indexing purposes.
Index (X) is a 24-bit number contained in a general
register specified by the program in the X field of the
instruction. It is included only in the address speci-
fied by the RX instruction format. The index can be
used to provide the address of an element within an
array. Thus, the RX format instructions permit double
Displacement (D) is a 12-bit number contained in
the instruction format. It is included in every address
computation. The displacement provides for relative
addressing up to 4095 bytes beyond the element or
base address. In array-type calculations the displace­
ment can be used to specify one of many items as­
sociated with an element. In the processing of records,
the displacement can be used to identify items within
a record.
In forming the address, the base address and index
are treated as unsigned 24-bit positive binary integers.
The displacement is similarly treated as a 12-bit posi­
tive binary integer. The three are added as 24-bit
binary numbers, ignoring overflow. Since every ad­
dress includes a base, the sum is always 24 bits long.
The address bits are numbered 8-31 corresponding to
the numbering of the base address and index bits in
the general register.
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