CSW STATUS STORED BY: Handling of Length START TEST HALT I/O I/O I/O I/O FLAGS ACTION AND INDICATION CONDITION INT.
CD CC SLI REGULAH OPERATION IMMEDIATE OPERATION Subchannel available 0 0 0 Stop,IL Stop, --
DE or attention in device B,d --,d '" --,d
Device working, CD available B B '" '" 0 0 1 Stop, -- Stop, -- 0 1 0 Stop,IL Chain command CU end or channel end in CU: 0 1 1 Chain command Chain command
for the addressed device B,d --,d '" --,d
for another device B,SM B,SM '" --,d
1 0 0 Stop,IL Stop, -- CU working B,SM B,SM '" '" 1 0 1 Stop,IL Stop, --
I 1 0 Stop,IL Stop, --
Interruption pend. in sub channel
1 1 1 Stop,IL Stop, --
for the addressed device
because of:
chaining terminated by
attention '" B,d '" B,d
other type of termination '" --,d '" --,cl
Subchannel working CU available '" '" '" CU working '" '" B,SM <I< Time and Method of Creating and Storing Status Indications WHEN WHEN UPON TERMINATION OF OPERATION DURING BY BY BY BY I/O STATUS Attention Status modifier Control unit end
Busy Channel end
Device end Unit check U nit exception
Program-controlled interruption
Incorrcct length Program check
Protection check Channel data check Channel control check
Interface control check Chaining check NOTES I/O IS IDLE CO CO CO co SUBCHANNEL AT
WORKING SUBCHANNEL CO C C C'" C C C C C C C co C co C'" co C'" C C C- The channel or the device can create or present the status
condition at the indicatcd time. A CSW or its status portion is
not necessarily stored at this time.
Conditions such as channel end amI devicc end are created at
the indicated time. Other conditions may have been created
previously, but are made accessible to the program only at thc
indicated time. Examples of such conditions arc program check
and channel data check, which are detected while data arc
transferred, but are made available to the program only with
channel end, unless the PCI flag or equipment malfunctioning
havc caused an interruption condition to be generated earlier. S- The status indication is stored in the CSW at the indicated
time.
An S appearing alone indicates that the condition has been
created previously. The letter C appearing with the S indicates
that the status condition did not necessarily exist previously in
the form that causes the program to be alerted, and may have AT CONTROL AT COMMAND START TEST HALT INTER- UNIT DEVICE CHAINING I/O I/O I/O RUPTION - - --- ---- C CO S S S C C CS CS CS S CO CS CS CS S C CS CS CS S C"'H C<>·!· Ct S S S CO c t Gr S S S C C C'" CS CS CS C C C'" CS S S C CS S S S S C'" CS S S S S S S CO CO C'" CS CS CS CS co CO C'" CS CS CS CS S S bccn created by the I/O instruction or I/O interruption. For
example, equipment malfunctioning may be detected during an I/O interruption, causing channel control check or interface
control check to be indicated; or a device such as the 2702 Transmission Control Unit may signal the control-un it-busy
condition in response ,to interrogation by an I/O instruction,
causing status modifier, busy, and control unit end to be indi­
catcd in the CSW. "'-The status condition generates or, in the case of channel
data check, may generate an interruption condition. Channel end and dcvice end do not result in interruption
conditions when command chaining is spccified and no unusual
conditions have bccn detected. 1"- This status indication can be created at the indicated time
only by an immediate operation.
H-When an operatioll1 on the selector channel has been termi­
natcd by HALT I/O, channel end indicates the termination of
the data-handling portion of the operation at the control unit.
Appendix G 155

Functions that May Differ Among Models Instruction Execution
In the editing operations, overlapping fields give un­
predictable results.
Equipment connected to the hold-in line of READ
DIRECT should be so constructed that the hold signal
will be removed when READ DIRECT is performed. Ex­
cessive duration of this instruction may result in in­
complete updating of the timer.
The purpose of the 12 field and the operand address
in the SI format of DIAGNOSE may be further defined
for a particular CPU and its appropriate diagnostic
procedures. Similarly the number of low-order address
bits that must be zero is further specified for a par­
ticular CPU. When the address does not have the re­
quired number of low-order zeros, a specification ex­
ception is recognized and causes a program interrup­
tion.
The diagnose operation is completed either by tak­
ing the next sequential instruction or by obtaining a
new psw from location 112. The diagnostic procedure
may affect the problem, supervisor, and interruptable
states of the CPU, and the contents of storage registers
and timer, as well as the progress of I/O operations. Instruction Termination Only one program interruption occurs for a given in­ struction. The old psw always identifies a valid cause.
This does not preclude simultaneous occurrence of
any other causes. Which of several causes is identified
may vary from one occasion to the next and from one
model to another.
When instruction execution is terminated by an in­
terruption, all, part, or none of the result may be
stored. The result data, therefore, are unpredictable.
The setting of the condition code, if called for, may
also be unpredictable. In general, the results of the
operation should not be used for further computation.
Cases of instruction termination for a program in­
terruption are:
Protection: The storage key of a result location does not match the protection key in the psw. The opera­
tion is terminated in the case of STORE MULTIPLE, READ
DIRECT, and variable-length operations. Protected stor­
age remains unchanged. The timing signals of READ
DIRECT may have been made available.
Addressing: An address specifies any part of data,
instruction, or control word outside the available stor­
age for the particular installation. The operation is
terminated. Data in storage remain unchanged, except
when designated by valid addresses.
156
Data: The sign or digit codes of operands in deci­
mal arithmetic, CONVERT TO BINARY, or editing opera­
tions are incorrect, or fields in decimal arithmetic over­
lap incorrectly, or the decimal multiplicand has too
many high-order significant digits. The operation is
terminated in all three cases. The condition code set­
ting, if called for, is unpredictable for protection, ad­
dressing, and data exceptions.
Exponent Overflow: The result exponent of an ADD, SUBTRACT, MULTIPLY, or DIVIDE overflows and the re­
sult fraction is not zero. The operation is terminated.
The condition code is set to 3 for ADD and SUBTRACT, and remains unchanged for MULTIPLY and DIVIDE. Machine-Check Interruption For a machine-check interruption, the old psw is
stored at location 48 with a zero interruption code.
The state of the CPU is scanned out into the storage
area starting with location 128 and extending through
as many words as are required by the given CPU. The
new psw is fetched from location 112. Proper execu­
tion of these steps depends Oil the nature of the ma­
chine check. A change in the machine-check mask bit
due to the loading of a new psw results in a change
in the treatment of machine checks. Depending upon
the nature of a machine check, the old treatment may
still be in force for several cycles. Machine checks that
occur in operations executed by I/O channels may
either cause a machine-check interruption or are re­
corded in the csw for that operation.
Instruction-Length Code The instruction-length code is predictable only for
program and supervisor-call interruptions. For I/O and
external interruptions, the interruption is not caused
by the last interpreted instruction, and the code is not
predictable for these classes of interruptions. For ma­
chine-check interruptions, the setting of the code is a
function of the malfunction and therefore unpredict­
able.
For the supervisor-call interruption the instruction­
length code is 1, indicating the halfword length of SUPERVISOR CALL; for the program interruptions, the
codes 1, 2, and 3 indicate the instruction length in
halfwords. The code 0 is reserved for program inter­
ruptions where the length of the instruction is not
available because of certain overlap conditions in in­
struction fetching. In those cases, the instruction ad­
dress in the old psw does not represent the next in­
struction address. The code 0 can
occur only for a program interruption caused by a
protected or unavailable data address.