Timer
Updating of the timer may be omitted whenI/O data
transmission approaches the limit of storage capa
bility.
SystemControl Panel The system-reset function may correct the parity of
general and floating-point registers, as well as the
parity of the psw.
The number of data switches is sufficient to allow
storing of a full physical storage word. Correct parity
generation is provided. In some models, either correct
or incorrect parity is generated under switch control.
The data in the storage, general register or floating
point register location, or the instruction-address part
of the psw as specified by the address switches and
the storage-select switch can be displayed by the dis
play key. When the location designated by the address
switches and storage-select switch is not available, the
displayed information is unpredictable. In some mod
els, the instruction address is permanently displayed
and hence is not explicitly selected.
When the· address-comparison switches are set to
the stop position, the address in the address switches
is compared against the value of the instruction ad
dress on some models, and against all addresses on
others. Comparison includes only that part of the in
struction address corresponding to the physical word
size of storage.
Comparison of the entire halfword instruction ad
dress is provided in some models, as is the ability to
compare data addresses.
The test light may be on when one or more diag
nostic functions under control ofDIAGNOSE are acti
vated, or when certain abnormal circuit breaker or
thermal conditions occur.Normal Channel Operation
Channel capacity depends on the wayI/O operations
are programmed and the activity in the rest of the
system. In view of this, an evaluation of the ability
of a specificI/O configuration to function concurrent
ly must be based on the application. Two systems em
ploying identical complements ofI/O devices may be
able to execute certain programs in common, but it
is possible that other programs requiring, for example,
data chaining may not run on one of the systems.
The time when the interruption due to thePCI flag
occurs depends on the model and the current activity.
The channel may cause the interruption an unpredict
able time after control of the operation is taken over
by the csw containing thePCI flag.
The content of the count field in a csw associated
with an interruption due to thePCI flag is unpredict
able. The content of the count field depends upon the
model and its current activity.
When the channel has established which device on
the channel will cause the nextI/O interruption, the
identity of the device is preserved in the channel. Ex
cept for conditions associated with termination of an
operation at the subchannel, the current assignment
of priority for interruptions among devices mayor
may not be canceled whenSTART r/o or TEST r/o is
issued to the channel, depending upon the model.
The assignment of priority among requests for in
terruption fromchannels is based on the type of chan
nel. The priorities of selector channels are in the order
of their addresses, with channel 1 having the highest
priority. The interruption priority of the multiplexor
channel is not fixed, and depends on the model and
the current activity in the channel.Channel Programming Errors
A data address referring to a location not provided in
the model normally causes program check when the
device offers a byte of data to be placed at the non
existent location or requests a byte from that location.
Models in which the channel does not have the ca
pacity to address 16,777,216 bytes of storagecause program check whenever the address is found to ex
ceed the addressing capacity of the channel.
In the following cases, action depends on the ad
dressing capacity of the model.
1. When the data address in the ccw deSignated
by theCAW exceeds the addressing capacity of the
model, theI/O operation is not initiated and the csw
is stored during the execution ofSTART rio. Normally
an invalid data address does not preclude the initi
ation of the operation.
2. When the data address in a ccw fetched during
command chaining exceeds the addressing capacity of
the model, theI/O operation is not initiated.
3. When a ccw fetched on data chaining contains
an address exceeding the addressing capacity of the
model and the device signals channel end immediate
ly upon transferring the last byte designated by the
preceding ccw, program check is indicated to the pro
gram. Normally, program check is not indicated un
less the device attempts to transfer one more byte of
data.
4. Data addresses are not checked for validity dur
ing skipping, except that the initial data address in
the ccw cannot exceed the addressing capacity of the
model.
When the channel detects program check or pro
tection check, the content of the count field in the
associated csw is unpredictable.
Appendix G 157
Updating of the timer may be omitted when
transmission approaches the limit of storage capa
bility.
System
general and floating-point registers, as well as the
parity of the psw.
The number of data switches is sufficient to allow
storing of a full physical storage word. Correct parity
generation is provided. In some models, either correct
or incorrect parity is generated under switch control.
The data in the storage, general register or floating
point register location, or the instruction-address part
of the psw as specified by the address switches and
the storage-select switch can be displayed by the dis
play key. When the location designated by the address
switches and storage-select switch is not available, the
displayed information is unpredictable. In some mod
els, the instruction address is permanently displayed
and hence is not explicitly selected.
When the· address-comparison switches are set to
the stop position, the address in the address switches
is compared against the value of the instruction ad
dress on some models, and against all addresses on
others. Comparison includes only that part of the in
struction address corresponding to the physical word
size of storage.
Comparison of the entire halfword instruction ad
dress is provided in some models, as is the ability to
compare data addresses.
The test light may be on when one or more diag
nostic functions under control of
vated, or when certain abnormal circuit breaker or
thermal conditions occur.
Channel capacity depends on the way
are programmed and the activity in the rest of the
system. In view of this, an evaluation of the ability
of a specific
ly must be based on the application. Two systems em
ploying identical complements of
able to execute certain programs in common, but it
is possible that other programs requiring, for example,
data chaining may not run on one of the systems.
The time when the interruption due to the
occurs depends on the model and the current activity.
The channel may cause the interruption an unpredict
able time after control of the operation is taken over
by the csw containing the
The content of the count field in a csw associated
with an interruption due to the
able. The content of the count field depends upon the
model and its current activity.
When the channel has established which device on
the channel will cause the next
identity of the device is preserved in the channel. Ex
cept for conditions associated with termination of an
operation at the subchannel, the current assignment
of priority for interruptions among devices mayor
may not be canceled when
issued to the channel, depending upon the model.
The assignment of priority among requests for in
terruption from
nel. The priorities of selector channels are in the order
of their addresses, with channel 1 having the highest
priority. The interruption priority of the multiplexor
channel is not fixed, and depends on the model and
the current activity in the channel.
A data address referring to a location not provided in
the model normally causes program check when the
device offers a byte of data to be placed at the non
existent location or requests a byte from that location.
Models in which the channel does not have the ca
pacity to address 16,777,216 bytes of storage
ceed the addressing capacity of the channel.
In the following cases, action depends on the ad
dressing capacity of the model.
1. When the data address in the ccw deSignated
by the
model, the
is stored during the execution of
an invalid data address does not preclude the initi
ation of the operation.
2. When the data address in a ccw fetched during
command chaining exceeds the addressing capacity of
the model, the
3. When a ccw fetched on data chaining contains
an address exceeding the addressing capacity of the
model and the device signals channel end immediate
ly upon transferring the last byte designated by the
preceding ccw, program check is indicated to the pro
gram. Normally, program check is not indicated un
less the device attempts to transfer one more byte of
data.
4. Data addresses are not checked for validity dur
ing skipping, except that the initial data address in
the ccw cannot exceed the addressing capacity of the
model.
When the channel detects program check or pro
tection check, the content of the count field in the
associated csw is unpredictable.
Appendix G 157