Updating of the timer may be omitted when I/O data
transmission approaches the limit of storage capa­
System Control Panel The system-reset function may correct the parity of
general and floating-point registers, as well as the
parity of the psw.
The number of data switches is sufficient to allow
storing of a full physical storage word. Correct parity
generation is provided. In some models, either correct
or incorrect parity is generated under switch control.
The data in the storage, general register or floating­
point register location, or the instruction-address part
of the psw as specified by the address switches and
the storage-select switch can be displayed by the dis­
play key. When the location designated by the address
switches and storage-select switch is not available, the
displayed information is unpredictable. In some mod­
els, the instruction address is permanently displayed
and hence is not explicitly selected.
When the· address-comparison switches are set to
the stop position, the address in the address switches
is compared against the value of the instruction ad­
dress on some models, and against all addresses on
others. Comparison includes only that part of the in­
struction address corresponding to the physical word
size of storage.
Comparison of the entire halfword instruction ad­
dress is provided in some models, as is the ability to
compare data addresses.
The test light may be on when one or more diag­
nostic functions under control of DIAGNOSE are acti­
vated, or when certain abnormal circuit breaker or
thermal conditions occur. Normal Channel Operation
Channel capacity depends on the way I/O operations
are programmed and the activity in the rest of the
system. In view of this, an evaluation of the ability
of a specific I/O configuration to function concurrent­
ly must be based on the application. Two systems em­
ploying identical complements of I/O devices may be
able to execute certain programs in common, but it
is possible that other programs requiring, for example,
data chaining may not run on one of the systems.
The time when the interruption due to the PCI flag
occurs depends on the model and the current activity.
The channel may cause the interruption an unpredict­
able time after control of the operation is taken over
by the csw containing the PCI flag.
The content of the count field in a csw associated
with an interruption due to the PCI flag is unpredict­
able. The content of the count field depends upon the
model and its current activity.
When the channel has established which device on
the channel will cause the next I/O interruption, the
identity of the device is preserved in the channel. Ex­
cept for conditions associated with termination of an
operation at the subchannel, the current assignment
of priority for interruptions among devices mayor
may not be canceled when START r/o or TEST r/o is
issued to the channel, depending upon the model.
The assignment of priority among requests for in­
terruption from channels is based on the type of chan­
nel. The priorities of selector channels are in the order
of their addresses, with channel 1 having the highest
priority. The interruption priority of the multiplexor
channel is not fixed, and depends on the model and
the current activity in the channel. Channel Programming Errors
A data address referring to a location not provided in
the model normally causes program check when the
device offers a byte of data to be placed at the non­
existent location or requests a byte from that location.
Models in which the channel does not have the ca­
pacity to address 16,777,216 bytes of storage cause program check whenever the address is found to ex­
ceed the addressing capacity of the channel.
In the following cases, action depends on the ad­
dressing capacity of the model.
1. When the data address in the ccw deSignated
by the CAW exceeds the addressing capacity of the
model, the I/O operation is not initiated and the csw
is stored during the execution of START rio. Normally
an invalid data address does not preclude the initi­
ation of the operation.
2. When the data address in a ccw fetched during
command chaining exceeds the addressing capacity of
the model, the I/O operation is not initiated.
3. When a ccw fetched on data chaining contains
an address exceeding the addressing capacity of the
model and the device signals channel end immediate­
ly upon transferring the last byte designated by the
preceding ccw, program check is indicated to the pro­
gram. Normally, program check is not indicated un­
less the device attempts to transfer one more byte of
4. Data addresses are not checked for validity dur­
ing skipping, except that the initial data address in
the ccw cannot exceed the addressing capacity of the
When the channel detects program check or pro­
tection check, the content of the count field in the
associated csw is unpredictable.
Appendix G 157
When a programming error occurs in the inform a -
tion placed in the CAW or ccw and the addressed
channel or sub channel is working, either condition
code 1 or 2 may be set, depending on the model.
Similarly, either code 1 or 3 may be set when a pro­
gramming error occurs and a part of the addressed I/O system is not operational.
When a programming error occurs and the ad­
dressed device contains an interruption condition,
with the channel and sub channel in the available
state, START I/O mayor may not clear the interruption
condition, depending on the type of error and the
model. If the instruction has caused the device to be
interrogated, as indicated by the presence of the busy
bit in the csw, the interruption condition has been
cleared, and the csw contains program check, as well
as the status from the device.
When the channel detects several error conditions,
all conditions may be indicated or only one may ap­
pear in the csw, depending on the condition and the
model. Equipment Errors Parity errors detected by the channel on data sent to
or received from the I/O device on some models cause
the current operation to be terminated. When the
channel and the CPU share common equipment, parity
errors on data may cause malfunction reset to be per­
formed. The recovery procedure in the channel and
subsequent state of the sub channel upon a malfunc­
tion reset depend on the model.
Detection of channel control check or interface con­
trol check causes the current operation, if any, to be
immediately terminated and causes the channel to per­
form the malfunction-reset function. The recovery pro­
cedure in the channel and the subsequent state of the
sub channel upon a malfunction reset depend on the
The contents of the csw, as well as the address in
the psw identifying the I/O device, are unpredictable
upon the detection of a channel-control-check con­
Execution of malfunction reset in the channel de­
pends on the type of error and model. It may cause
all operations in the channel to be terminated and all
operational subchannels to be reset to the available
state. The channel may send the malfunction-reset
signal to the device connected to the channel at the
time the malfunctioning is detected, or a channel shar­
ing common equipment with the CPU may send the
system-reset signal to all devices attached to the chan­
The method of processing a request for interruption
due to equipment malfunctioning, as indicated by the
presence of the channel-data-check, channel-control­
check, and interface-control-check conditions, depends
on the model. In channels sharing common equipment
with the CPU, malfunctioning detected by the channel
may be indicated by the machine-check interruption.
Previous Page Next Page