The fixed-point instruction set performs binary arith metic on operands serving as addresses, index quanti

ties, and counts, as well as fixed-point data. In general,

both operands are signed and 32 bits long. Negative

quantities are held in two's-complement form.One operand is always in one of the 16 general registers;

the other operand may be in main storage or in a

general register.

The instruction set provides for loading, adding,

subtracting, comparing, multiplying, dividing, and

storing, as well as for the sign control, radix conver

sion, and shifting of fixed-point operands. The entire

instruction set is included in the standard instruction

set.

The condition code is set as a result of allsign control, add, subtract, compare, and shift operations.

Data Format

Fixed-point numbers occupy a fixed-length format

consisting of a one-bit sign followed by the integer

field. When held in one of the general registers, a

fixed-point quantity has a 31-bit integer field andoc cupies all 32 bits of the register. Some multiply, divide,

and shift operations use an operand consisting of 64

bits with a 63-bit integer field. These operands are

located in a pair of adjacent general registers and are

addressed by an even address referring to theleft most register of the pair. The sign-bit position of the

rightmost register contains part of the integer. Inreg ister-to-register operations the same register may be

specified for both operand locations.

Fullword Fixed-Point Number151 Integer o 1 31

Halfword Fixed-Point NumberI s\ Integer o 1 15

Fixed-point data in main storage occupy a 32-bit word

or a 16-bit halfword, with a binary integer field of 31

or 15 bits, respectively. The conversion instructions

Fixed-Point Arithmetic

use a 64-bit decimal field. These data must be located

on integral storage boundaries for these units ofinfor mation, that is, double-word, fullword, or halfword

operands must bc addressed with three, two, or one

low-ordcr address bit ( s) set to zero.

A halfword operand in main storage is extended to

a fullword as the operand is fetched from storage.

Subsequently, the operand participates as a full word

operand.

Number Representation

All fixed-point operands are treated as signed integers.Positive numbers are represented in true binary nota tion with the sign bit set to zero. Negative numbers

are represented in two's-complement notation with a

one in the sign bit. The two's complement of anum ber is obtained by inverting each bit of the number

and adding a one in the low-order bit position.

This type of number representation can be consider

ed the low-order portion of an infinitely long represen

tation of the number. When the number is positive, all

bits to the left of the most significant bit of thenum ber, including the sign bit, are zeros. When the num ber is negative, all these bits, including the sIgn bit,

are ones. Therefore, when an operand must beex tended with high-order bits, the expansion is achieved

by prefixing a field in which each bit is set equal to

the high-order bit of the operand.

Two's-complement notation does not include anega tive zero. It has a number range in which the set of

negative numbers is one larger than the set of positive

numbers. The maximum positive number consists of

an all-one integer field with a sign bit of zero, whereas

the maximum negative number consists of an all-zero

integer field with a one-bit for sign.

TheCPU cannot represent the complement of the

maximum negative number. When an operation, such

as a subtraction from zero, produces the complement

of the maximum negative number, the number remains

unchanged, and afixed-pOint overflow exception is

recognized. An overflow does not result, however,

when the number is complemented and the finalre suIt is within the representable range. An example of

this case is a subtraction from minus one. The product

of two maximum negative numbers is representable as

a double-length positive number.

Fixed-Point Arithmetic 23

ties, and counts, as well as fixed-point data. In general,

both operands are signed and 32 bits long. Negative

quantities are held in two's-complement form.

the other operand may be in main storage or in a

general register.

The instruction set provides for loading, adding,

subtracting, comparing, multiplying, dividing, and

storing, as well as for the sign control, radix conver

sion, and shifting of fixed-point operands. The entire

instruction set is included in the standard instruction

set.

The condition code is set as a result of all

Data Format

Fixed-point numbers occupy a fixed-length format

consisting of a one-bit sign followed by the integer

field. When held in one of the general registers, a

fixed-point quantity has a 31-bit integer field and

and shift operations use an operand consisting of 64

bits with a 63-bit integer field. These operands are

located in a pair of adjacent general registers and are

addressed by an even address referring to the

rightmost register contains part of the integer. In

specified for both operand locations.

Fullword Fixed-Point Number

Halfword Fixed-Point Number

Fixed-point data in main storage occupy a 32-bit word

or a 16-bit halfword, with a binary integer field of 31

or 15 bits, respectively. The conversion instructions

Fixed-Point Arithmetic

use a 64-bit decimal field. These data must be located

on integral storage boundaries for these units of

operands must bc addressed with three, two, or one

low-ordcr address bit ( s) set to zero.

A halfword operand in main storage is extended to

a fullword as the operand is fetched from storage.

Subsequently, the operand participates as a full word

operand.

Number Representation

All fixed-point operands are treated as signed integers.

are represented in two's-complement notation with a

one in the sign bit. The two's complement of a

and adding a one in the low-order bit position.

This type of number representation can be consider

ed the low-order portion of an infinitely long represen

tation of the number. When the number is positive, all

bits to the left of the most significant bit of the

are ones. Therefore, when an operand must be

by prefixing a field in which each bit is set equal to

the high-order bit of the operand.

Two's-complement notation does not include a

negative numbers is one larger than the set of positive

numbers. The maximum positive number consists of

an all-one integer field with a sign bit of zero, whereas

the maximum negative number consists of an all-zero

integer field with a one-bit for sign.

The

maximum negative number. When an operation, such

as a subtraction from zero, produces the complement

of the maximum negative number, the number remains

unchanged, and a

recognized. An overflow does not result, however,

when the number is complemented and the final

this case is a subtraction from minus one. The product

of two maximum negative numbers is representable as

a double-length positive number.

Fixed-Point Arithmetic 23