Instructions
The fixed-point arithmetic instructions and their mne-
monics, formats, and operation codes are listed in the
following table. The table also indicates which instruc-
tions are not included in the small binary instruction
set, when the condition code is set, and the exceptional
conditions that cause a program interruption.
NAMEMNEMONIC Load LR
Load L
Load Halfword LH
Load and Test LTR
LoadComplement LCR Load Positive LPR Load Negative LNR
Load Multiple LM
Add AR
Add A
Add Halfword All
Add Logical ALR
Add Logical ALSubtract SR Subtract S Subtract Halfword SH Subtract Logical SLR Subtract Logical SL Compare CR Compare C Compare Halfword CH Multiply MR
Multiply M
Multiply Halfword MH
Divide DR
Divide DConvert to Binary CVB Convert to Decimal CVD Store ST Store Halfword STH Store Multiple STM Shift Left Single SLA Shift Right Single SRA Shilt Left Double SLDA Shift Right Double SRDA Addressing exception
Condition code is set
Data exception
TYPE
RR
RX
RX
RR
RR
RR
RRRS RR
RX
RX
RR
RX
RR
RX
RX
RR
RX
RR
RX
RX
RR
RX
RX
RR
RX
RX
RX
RX
RXRS RS RS RS RS NOTES A C D
IF
IKP S Fixed-Point overflow exception
Fixed-point divide exceptionProtection exception
Specification exception
Programming NoteEXCEPTIONS A,S A,S C C IF C IF C A,S C IF C A,S, IF C A,S, IF C C A,S C IF C A,S, IF C A,S, IF C C A,S C C A,S C A,S S A,S A,S S, IK A,S, IK A,S,D,IK P,A,S P,A,S P,A,S P,A,S C IF C C S, IF C S CODE 18
58
48
12
1310 11
98
lA
5A
4A
IE
5E
IB
5B
4B
IF
5F
19
59
49
Ie5C 4C ID
5D
4F
4E50 40 90 8B
8A
8F
8E
The logical comparisons, shifts, and connectives, as
well asLOAD ADDRESS, BRANCH ON COUNT, BRANCH ON INDEX HIGH, and BRANCH ON INDEX LOW OR EQUAL, also
may be used in fixed-point calculations.
Load
LR RRI 18 R1 R2 0 7 8 11 12 15
L RXI 58 R1
X
2
B2 D20 7 8 11 12 1516 1920 31
The second operand is placed in the first operand loca
tion. The second operand is not changed.
Condition Code: The code remains unchanged.
Program Interruptions:
Addressing (L only)
Specification (L only)
Load Halfword
LH RX
48
7 8 11 12 15 16 1 920 31
The halfword second operand is placed in the first
operand location.
The halfword second operand is expanded to a full
word by propagating the sign-bit value through the
16 high-order bit positions. Expansion occurs after the
operand is obtained from storage and before insertion
in the register.
Program Interruptions:
Addressing
Specification
Load and Test
LTR RR
12
7 8 11 12 15
The second operand is placed in the first operand loca
tion, and the sign and magnitude of the second op
erand determine the condition code. The second op
erand is not changed.Fixed-Point Arithmetic 25
The fixed-point arithmetic instructions and their mne-
monics, formats, and operation codes are listed in the
following table. The table also indicates which instruc-
tions are not included in the small binary instruction
set, when the condition code is set, and the exceptional
conditions that cause a program interruption.
NAME
Load L
Load Halfword LH
Load and Test LTR
Load
Load Multiple LM
Add AR
Add A
Add Halfword All
Add Logical ALR
Add Logical AL
Multiply M
Multiply Halfword MH
Divide DR
Divide D
Condition code is set
Data exception
TYPE
RR
RX
RX
RR
RR
RR
RR
RX
RX
RR
RX
RR
RX
RX
RR
RX
RR
RX
RX
RR
RX
RX
RR
RX
RX
RX
RX
RX
IF
IK
Fixed-point divide exception
Specification exception
Programming Note
58
48
12
13
98
lA
5A
4A
IE
5E
IB
5B
4B
IF
5F
19
59
49
Ie
5D
4F
4E
8A
8F
8E
The logical comparisons, shifts, and connectives, as
well as
may be used in fixed-point calculations.
Load
LR RR
L RX
X
2
B2 D2
The second operand is placed in the first operand loca
tion. The second operand is not changed.
Condition Code: The code remains unchanged.
Program Interruptions:
Addressing (L only)
Specification (L only)
Load Halfword
LH RX
48
7 8 11 12 15 16 1 9
The halfword second operand is placed in the first
operand location.
The halfword second operand is expanded to a full
word by propagating the sign-bit value through the
16 high-order bit positions. Expansion occurs after the
operand is obtained from storage and before insertion
in the register.
Program Interruptions:
Addressing
Specification
Load and Test
LTR RR
12
7 8 11 12 15
The second operand is placed in the first operand loca
tion, and the sign and magnitude of the second op
erand determine the condition code. The second op
erand is not changed.