Resulting Condition Code:
o
1 Difference is not zero (no carry)
2 Difference is zero (carry)
3 Difference is not zero (carry) Program Interruptions:
Addressing (SL only)
Specification (SL only)
Programming Note
A zero difference cannot be obtained without a carry
out of the sign position. Compare CR RR I 19 R, R2 0 7 8 11 12 15
C
RX I 59 R, X
2
B2 0 7 8 11 12 1516 1920 31
The first operand is compared with the second op­
erand, and the result determines the setting of the
condition code.
Comparison is algebraic, treating both comparands
as 32-bit signed integers. Operands in registers or
storage are not changed.
Resulting Condition Code:
o Operands are equal
1 First operand is low
2 First operand is high
3 Program Interruptions:
Addressing (C only)
Specification (C only) Compare Halfword CH RX
49
7 8 11 12 15 16 1920 31
The first operand is compared with the halfword sec- ' ond operand, and the result determines the setting of
the condition code.
The halfword second operand is expanded to a full­
word before the comparison by propagating the sign­
bit value through the 16 high-order bit positions.
Comparison is algebraic, treating both comparands
as 32-bit signed integers. Operands in registers or
storage are not changed.
Resulting Condition Code:
o Operands are equal
1 First operand is low
2 First operand is high
3 Program Interruptions:
Addressing
Specification Multiply MR RR
1C
78 1112 15 M RX
5C
7 8 11 1 2 15 1 6 1 9 20 J
31
The product of the multiplier (the second operand)
and the multiplicand (the first operand) replaces the
multiplicand.
Both multiplier and multiplicand are 32-bit signed
integers. The product is always a 64-bit signed integer
and occupies an even/odd register pair. Because the
multiplicand is replaced by the product, the Rl field
of the instruction must refer to an even-numbered reg­
ister. A specification exception occurs when Rl is odd.
The multiplicand is taken from the odd register of the
pair. The content of the even-numbered register re­
placed by the product is ignored, unless the register
contains the multiplier. An overflow cannot occur.
The sign of the product is determined by the rules
of algebra from the multiplier and multiplicand sign,
except that a zero result is always positive.
Condition Code: The code remains unchanged. Program Interruptions:
Addressing (M only)
Specification
Programming Note
The significant part of the product usually occupics 62
bits or fewer. Only when two maximum negative
numbers are multiplied are 63 significant product bits
formed. Since two's-complement notation is used, the
sign bit is extended right until the first significant
product digit is encountered.
Fixed-Point Arithmetic 29

Multiply Halfword
MH RX 7 8 11 12 15 16 1920 31
The product of the halfword multiplier (second op­
erand) and multiplicand (first operand) replaces the
multiplicand.
Both multiplicand and product are 32-bit signed
integers and may be located in any general register.
The half word multiplier is expanded to a fullword
before multiplication by propagating the sign-bit value
through the 16 high-order bit positions. The multi­
plicand is replaced by the low-order part of the prod­
uct. The bits to the left of the 32 low-order bits are
not tested for significance; no overflow indication is
given.
The sign of the product is determined by the rules
of algebra from the multiplier and multiplicand sign,
except that a zero result is always positive.
Condition Code: The code remains unchanged. Program Interruptions:
Addressing S pecifica tion
Programming Note
The significant part of the product usually occupies 46
bits or fewer, the exception being 47 bits when both
operands are maximum negative. Since the low-order
32 bits of the product are stored unchanged, ignoring
all bits to the left, the sign bit of the result may differ
from the true sign of the product in the case of over­
flow.
Divide
DR RR
1D
7 8 11 12 15
D
RX
5D
7 8 11 1 2 15 16 1 9 20 31
The dividend (first operand) is divided by the divisor
(second operand) and replaced by the quotient and
remainder.
The dividend is a 64-bit signed integer and occupies
the even/odd pair of registers specified by the Rl field
of the instruction. A specification exception occurs 30 when Rl is odd. A 32-bit signed remainder and a
32-bit signed quotient replace the dividend in the
even-numbered and odd-numbered registers, respec­
tively. The divisor is a 32-bit signed integer.
The sign of the quotient is determined by the rules
of algebra. The remainder has the same sign as the
dividend, except that a zero quotient or a zero re­
mainder is always positive. All operands and results
are treated as signed integers. When the relative
magnitude of dividend and divisor is such that the
quotient cannot be expressed by a 32-bit signed integ­
er, a fixed-point divide exception is recognized (a
program interruption occurs, no division takes place,
and the dividend remains unchanged in the gcneral
registers) .
Condition Code: The code remains unchanged. Program Interruptions:
Addressing (D only) S pecifica tion
Fixed-point divide
Programming Note
Division applies to fullword operands in storage only .. Convert to Binary eva RX
4F
7 8 11 12 15 16 1920 31
The radix of the second operand is changed from deci­
mal to binary, and the result is placed in the first
operand location. The number is treated as a right­
aligned signed integer both before and after conver­
sion.
The second operand has the packed decimal data
format and is checked for valid sign and digit codes.
Improper codes are a data exception and cause a pro­
gram interruption. The decimal operand occupies a
double-word storage field, which must be located on
an integral boundary. The low-order four bits of the
field represent the sign. The remaining 60 bits contain
15 binary-coded-decimal digits in true notation. The
packed decimal data format is described under "Deci­ mal Arithmetic." The result of the conversion is placed in the general
register specified by R l • The maximum number that
can be converted and still be contained in a 32-bit
register is 2,147,483,647; the minimum number is
-2,147,483,648. For any decimal number outside this
range, the operation is completed by placing the 32
low-order binary bits in the register; a fixed-point